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CS4298
SoundFusion(R) Audio/Modem Codec '97(AMC'97)
FEATURES
s AC `97 2.0 compatible s 20-bit stereo output and 18-bit stereo input codec with fixed 48 kHz sampling rate s 20-bit output and 18-bit input dual modem AFE with fixed 48 kHz sampling rate s Dedicated ADC for handset or speakerphone s Four analog line-level stereo inputs for connection from LINE IN, CD, VIDEO, and AUX s High quality pseudo-differential CD input s Dual stereo line level output with independent 6bit volume control s 10 General Purpose I/O pins for Modem DAA controls s IEC-958 Digital Output (S/PDIF) s Meets or exceeds Microsoft's (R) PC 98 and PC 99 audio performance requirements s CrystalClearTM 3D Stereo Enhancement ORDERING INFORMATION CS4298-KQ 64-pin TQFP CS4298-JQ 64-pin TQFP
DESCRIPTION
The CS4298 is an AC `97 compatible Audio/Modem Codec designed for PC multimedia systems. Using the industry leading CrystalClearTM deltasigma and mixed signal technology, the CS4298 is ideal for PC 98-compliant desktop, notebook, and entertainment PCs, where high-quality audio and modem features are required.The CS4298 offers four channels of D/A and A/D conversion along with analog mixing and 3D processing. For multichannel audio systems, the CS4298 can provide four audio channels. For combined audio/modem systems, the CS4298 can provide a modem AFE, voice codec, and stereo audio codec..
10x10x1.4mm 10x10x1.4mm
MAIN D/A CONVERTERS PCM_OUT MIC1 MIC2 LINE 2 / VOL MIC SELECT +20dB VOL DAC VOL
2
/ PCM OUT PATH MUTE
MUTE STEREO INPUT MIXER
3D
MASTER VOLUME OUTPUT BUFFER 2
MUTE
STEREO OUTPUT MIXER
VOL
/
LINE_OUT
CD
2
/
VOL
MUTE
VIDEO
2
/
VOL
MUTE
ALTERNATE VOLUME VOL STEREO TO MONO MIXER 2 OUTPUT BUFFER 2 / ALT_LINE_OUT
AUX
2
/
VOL
MUTE
/
VOL
MUTE
MAIN ADC GAIN ADC INPUT MUX VOL MUTE ADC
SDATA_OUT RESET# SYNC Mode Control MRX+ (loopback) MTX+ MRX(loopback) MTXVref HRX+ (loopback) HTX+ VOL ADC HRX(loopback) HTXVref VOL HRXDAC VOL ADC VOL MRX+ HRX+ -+ Class AB Dif out +DAC
SDATA_IN
AC-Link Interface
3 / MRX-+ Class AB Dif out +-
BIT_CLK 10 / GPIO
MTX+
MTX-
HTX+
HTX-
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 1999 (All Rights Reserved)
AUG `99 DS315PP2 1
CS4298
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5 AUDIO ANALOG CHARACTERISTICS.................................................................................... 5 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 6 RECOMMENDED OPERATING CONDITIONS ....................................................................... 6 MIXER CHARACTERISTICS.................................................................................................... 6 MODEM CHARACTERISTICS ................................................................................................. 7 SERIAL PORT TIMING............................................................................................................. 9 2. GENERAL DESCRIPTION ..................................................................................................... 12 2.1 Overview ........................................................................................................................... 12 2.2 Modes of Operation .......................................................................................................... 12 2.2.1 Mode 0 .................................................................................................................... 12 2.2.2 Mode 1 .................................................................................................................... 12 2.2.3 Mode 2 .................................................................................................................... 12 2.2.4 Mode 3 .................................................................................................................... 12 3. DIGITAL SECTION ................................................................................................................. 13 3.1 AC-Link ............................................................................................................................. 13 3.2 Control registers................................................................................................................ 13 4. ANALOG SECTION ................................................................................................................ 14 4.1 Audio Output Mixer ........................................................................................................... 14 4.2 Audio Input Mux ................................................................................................................ 14 4.3 Audio Input Mixer .............................................................................................................. 14 4.4 Audio Volume Control ....................................................................................................... 14 5. AC `97 ..................................................................................................................................... 16 5.1 AC `97 Frame Definition.................................................................................................... 16 5.2 AC-Link Serial Data Output Frame ................................................................................... 16 5.3 AC-Link AudioOutput Frame............................................................................................. 17 5.3.1 Serial Data Output Slot Tags (Slot 0)............................................................................. 17 5.3.2 Register Address (Slot 1)............................................................................................... 17 5.3.3 Register Write Data (Slot 2) ........................................................................................... 18 5.3.4 Playback Data (Slots 3-11) ............................................................................................ 18 5.3.5 GPIO Data (Slot12)........................................................................................................ 18 5.4 AC-Link Audio Input Frame............................................................................................... 18 5.4.1 Serial Data Input Slot Tag Bits (Slot 0) ......................................................................... 18 5.4.2 Read-Back Address Port (Slot 1)................................................................................... 19 5.4.3 Read-Back Data Port (Slot 2) ........................................................................................ 19 5.4.4 PCM Capture Data (Slot 3-11)....................................................................................... 19 5.4.5 GPIO Pin Status (Slot 12) .............................................................................................. 19
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic webbiest or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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5.5 AC '97 Reset Modes......................................................................................................... 20 5.5.1 Cold AC `97 Reset................................................................................................... 20 5.5.2 Warm AC '97 Reset ................................................................................................ 20 5.5.3 AC '97 Register Reset............................................................................................. 20 5.6 AC-Link Protocol Violation - Loss of SYNC ...................................................................... 20 6. REGISTER INTERFACE ........................................................................................................ 21 6.1 Register Descriptions ....................................................................................................... 23 6.1.1 Reset (Index 00h) ......................................................................................................... 23 6.1.2 Master Volume (Index 02h) .......................................................................................... 23 6.1.3 Alternate Volume (Index 04h) ....................................................................................... 24 6.1.4 Microphone Volume (Index 0Eh) ................................................................................... 24 6.1.5 Stereo Analog Mixer Input Gain (Index's 10h - 18h) ..................................................... 25 6.1.6 Input Mux Select (Index 1Ah) ........................................................................................ 25 6.1.7 Record Gain (Index 1Ch)............................................................................................... 26 6.1.8 Record Gain Microphone (Index 1Eh) ........................................................................... 26 6.1.9 General Purpose (Index 20h) ........................................................................................ 26 6.1.10 3D Control (Index 22h) ................................................................................................ 26 6.1.11 Power Down Control/Status (Index 26h) ..................................................................... 27 6.1.12 Extended Audio ID (Index 28h) .................................................................................. 28 6.1.13 Extended Audio Status / Control (Index 2Ah) ............................................................. 28 6.1.14 PCM Front DAC Rate (Index 2Ch) ........................................................................... 29 6.1.15 PCM Surround DAC Rate (Index 2Eh) ..................................................................... 29 6.1.16 PCM LFE DAC Rate (Index 30h) .............................................................................. 29 6.1.17 PCM LR ADC Rate (Index 32h)................................................................................... 29 6.1.18 PCM MIC ADC Rate (Index 34h)................................................................................. 29 6.1.19 Center LFE Volume (Index 36h) .................................................................................. 30 6.1.20 LR Surround Volume (Index 38h) ................................................................................ 30 6.1.21 Extended Modem ID (Index 3Ch) ............................................................................... 30 6.1.22 Extended Modem ID (Index 3Eh) ............................................................................... 31 6.1.23 Line 1 DAC/ADC Rate (Index 40h) .............................................................................. 31 6.1.24 Line 2 DAC/ADC Rate (Index 42h) .............................................................................. 31 6.1.25 Handset DAC/ADC Rate (Index 44h) .......................................................................... 32 6.1.26 Line 1 DAC/ADC Level (Index 46h) ............................................................................. 32 6.1.27 Line 2 DAC/ADC Level (Index 48h) ............................................................................. 32 6.1.28 Handset DAC/ADC Level (Index 4Ah) ......................................................................... 32 6.1.29 GPIO Pin Configuration (Index 4Ch) ........................................................................... 33 6.1.30 GPIO Pin Polarity/Type Configuration (Index 4Eh) ..................................................... 33 6.1.31 GPIO Pin Sticky (Index 50h)........................................................................................ 33 6.1.32 GPIO Pin Wakeup Mask (Index 4Ch) ......................................................................... 34 6.1.33 GPIO Pin Status (Index 54h) ....................................................................................... 34 6.1.34 Misc. Modem AFE Status (Index 56h) ........................................................................ 34 6.1.35 AC Mode Control (Index 5Eh) ..................................................................................... 35 6.1.36 S/PDIF Control (Index 68h) ......................................................................................... 35 6.1.37 Vendor ID1 (Index 7Ch)............................................................................................... 36 6.1.38 Vendor ID2 (Index 7Eh) ............................................................................................... 36 7. ANALOG HARDWARE DESCRIPTION ................................................................................. 37 7.1 Line-Level Inputs .............................................................................................................. 37 7.2 Microphone Level Inputs .................................................................................................. 38 7.3 Line Level Outputs............................................................................................................ 38 7.4 Consumer IEC-958 Digital Interface (S/PDIF) .................................................................. 39 7.5 Miscellaneous Analog Signals .......................................................................................... 39 7.6 Power Supplies................................................................................................................. 40 7.7 Hybrid Interface ................................................................................................................ 41
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8. PIN DESCRIPTIONS .............................................................................................................. 42 8.1 g2 ..................................................................................................................................... 43 8.2 Analog I/O Pins ................................................................................................................ 45 8.3 Filter and Reference Pins ................................................................................................ 46 8.4 Modem/Telephony ........................................................................................................... 47 8.5 Power Supplies ................................................................................................................ 48 9. PARAMETER AND TERM DEFINITIONS .............................................................................. 49 10. REFERENCES ...................................................................................................................... 50 11. PACKAGE DIMENSIONS ..................................................................................................... 51
LIST OF FIGURES
Figure 1. Power Up Timing............................................................................................................ 10 Figure 2. Clocks ............................................................................................................................ 10 Figure 3. Codec Ready from Startup or Fault Condition ............................................................... 10 Figure 4. Data Setup and Hold ...................................................................................................... 11 Figure 5. PR4 Powerdown ............................................................................................................ 11 Figure 6. Test Mode ...................................................................................................................... 11 Figure 7. AC-link Connections....................................................................................................... 13 Figure 8. Mixer Diagram................................................................................................................ 15 Figure 9. AC-link Input and Output Framing.................................................................................. 16 Figure 10. Line Inputs.................................................................................................................... 37 Figure 11. Differential CDROM In ................................................................................................. 37 Figure 12. PC `99 Microphone Pre-amplifier ................................................................................. 38 Figure 13. Headphones Driver ...................................................................................................... 39 Figure 14. IEC-958 Interface Examples ........................................................................................ 40 Figure 15. Voltage Regulator ........................................................................................................ 40 Figure 16. Hybrid Circuit Secondary ............................................................................................ 41
LIST OF TABLES
Table 1. Mixer Registers ............................................................................................................... 21 Table 2. Alternate Line-Out and Master Mono Attenuation ........................................................... 24 Table 3. Analog Mixer Input Gain Values...................................................................................... 24 Table 4. Stereo Volume Register Index ........................................................................................ 25 Table 5. Input Mux Selection ......................................................................................................... 25 Table 6. 6 Channel Volume Attenuation........................................................................................ 30 Table 7. GPIO Input/Output Configuration .................................................................................... 33 Table 8. Misc. Modem Configuration............................................................................................. 34 Table 9. Slot Assignments............................................................................................................ 35 Table 10. Reg. 7Eh Defined Part ID's ........................................................................................... 36
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1. CHARACTERISTICS AND SPECIFICATIONS
AUDIO ANALOG CHARACTERISTICS (Standard test conditions unless otherwise noted:
Tambient = 25 C, AVdd = 5.0 V 5%, DVdd = 3.3 V 5%; 1 kHz Input Sine wave; Sample Frequency, Fs = 48 kHz; ZAL=10 k/680 pF load CDL = 18 pF load (Note 1); Measurement bandwidth is 20 Hz - 20 kHz, 18-bit linear coding for ADC, 20-bit linear coding for DAC; Mixer registers set for unity gain. Parameter (Note 2) Full Scale Analog Input Voltage Line Inputs Mic Inputs (20 dB=0) Mic Inputs (20 dB=1) Full Scale Output Voltage (Note 4) Line and Alternate Line Outputs Frequency Response Analog Ac = 0.5 dB FR DAC Ac = 0.5 dB ADC Ac = 0.5 dB Dynamic Range Stereo Analog inputs to LINE_OUT DR Mono Analog inputs to LINE_OUT DAC Dynamic Range ADC Dynamic Range DAC SNR (-20 dB FS input w/ CCIR-RMS filter on output) SNR Total Harmonic Distortion + Noise (-3 dB FS input signal): Line/Alternate Line Output THD+N DAC ADC (all inputs except phone/mic) ADC (phone/mic) Power Supply Rejection Ratio (1 kHz, 0.5 VRMS w/ 5 V DC offset)(Note 5) Interchannel Isolation Spurious Tone (Note 5) Input Impedance (Note 5) External Load Impedance Output Impedance (Note 5) Input Capacitance (Note 5) Vrefout CS4298-KQ Path Symbol (Note 3) Min Typ Max A-D A-D A-D D-A A-A D-A A-D A-A A-A D-A A-D D-A 0.91 1.00 0.91 1.00 0.091 0.10 0.91 20 20 20 90 85 85 85 1.0 95 90 90 90 63 1.13 20,000 20,000 20,000 CS4298-JQ Min Typ Max 1.13 20,000 20,000 20,000 Unit VRMS VRMS VRMS VRMS Hz Hz Hz dB FS A dB FS A dB FS A dB FS A dB
0.91 1.00 0.91 1.00 0.091 0.10 0.91 20 20 20 1.0 90 85 87 85 -
A-A D-A A-D A-D
40 70 10 10 2.0
-94 -86 -87 -87 60 87 -100 730 5 2.3
-80 -80 -80 -74 2.4
10 10 2.0
40 87 -100 730 5 2.3
-74 -74 -74 -74 2.4
dB FS A dB FS A dB FS A dB FS A dB dB dB FS k k W pF V
Notes: 1. ZAL refers to the analog output pin loading and C DL refers to the digital output pin loading. 2. Parameter definitions are given in the Parameter and Term Definitions section. 3. Path refers to the signal path used to generate this data. These paths are defined in the Parameter and Term Definition section. 4. Typical measured with ZAL = 47 k/680 pF load. 5. This specification is guaranteed by silicon characterization, it is not production tested.
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ABSOLUTE MAXIMUM RATINGS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V)
Parameter Power Supplies +3.3 V Digital +5 V Digital Analog (Supplies, Inputs, Outputs) (Except Supply Pins) (Except Supply Pins) Min -0.3 -0.3 -0.3 -10 -15 -0.3 -0.3 (Power Applied) -55 -65 Typ Max 6.0 6.0 6.0 750 10 15 AVdd+ 0.3 DVdd + 0.3 110 150 Unit V V V mW mA mA V V C C
Total Power Dissipation Input Current per Pin Output Current per Pin Analog Input voltage Digital Input voltage Ambient Temperature Storage Temperature
RECOMMENDED OPERATING CONDITIONS (AVss1 = AVss2 = DVss1 = DVss2 = 0 V)
Parameter Power Supplies +3.3 V Digital +5 V Digital Analog +3.3 V Digital +5 V Digital Analog Symbol DVdd1, DVdd2 DVdd1, DVdd2 AVdd1, AVdd2 DVdd1, DVdd2 DVdd1, DVdd2 AVdd1, AVdd2 Min 3.135 4.75 4.75 Typ 3.3 5 5 40 40 75 Max 3.465 5.25 5.25 52 52 97.5 70 Unit V V V mA mA mA C
Operating Current
Operating Ambient Temperature
0 (for CS4298-KQ only) Min -
MIXER CHARACTERISTICS
Mixer Gain Range Span Step Size
Parameter Line In, Aux, CD, Video, Mic1 Mic2, Line Out, Alternate Line Out All volume controls
Typ 46.5 94.5 1.5
Max -
Unit dB dB dB
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MODEM CHARACTERISTICS (Analog Transmitter Specifications: Tambient = 0 to 70 C, AVdd = 5.0 V; Sample Frequency, Fs = 48 kHz; Audio specifications for 20Hz - 5 kHz, actual digital filter may cutoff at 20 kHz, 600 differential load where applicable)
Parameter Min 20 (Note 5) 20 85 TBD 250 60 7.4 (Note 5) 6 (Note 5) (Note 5) (Note 5) 88 5.6 0.1 TBD 100 5000 0.125 Typical Max Units bits dB FS Hz dB1K dB FS Volts W W dB mA mV
Modem Analog Transmitter Characteristics Resolution
Dynamic Range Passband Passband Ripple Total Harmonic Distortion Full Scale Peak to Peak Output Voltage (TX+ to TX-) AC Output Impedance (TX+, TX-) Load Impedance (per pin) Power Supply Rejection (1kHz) Output Current (per pin) Offset (relative) Out of Band specifications (Tambient = 25 C, AVdd = 5 V; Sample Frequency, Fs = 48 kHz; measurement bandwidth 20 kHz - 1MHz, RL=600 , C L=33nF) (Note 5) Total Out of Band energy (20 kHz - 1 MHz) (Note 5) Highest 9kHz band (noise + tone) power (90 kHz - 2 MHz) (Note 5, 6)
-40 -30 -55
dB FS dBV dBV
Modem Analog Receiver Characteristics Resolution
Dynamic Range Passband Passband Ripple Total Harmonic Distortion Total Absolute Gain Accuracy Full Scale Peak to Peak Input Voltage (RX+ to RX-, differential) Gain = 0 Input Impedance (per pin) Offset (relative) Power Supply Rejection (Note 5) (Note 5) (Note 5) Gain = 0 Gain = 0
18 90 20 85 -5 2.8 15 6 40 60 +5 5000 0.125
bits dB FS Hz dB1K dB FS % Volts K mV dB
Notes: 6. This is the FCC specification for Out-of-Band energy at the telephone jack interface. 9 kHz refers to the bin size of an FFT performed over the entire range. The amount of noise plus tone power in each 8kHz bin must be less than -55dBV.
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CS4298
DIGITAL CHARACTERISTICS (AVss = DVss = 0 V)
Parameter Symbol Vil Vih Voh Vol Min Typ Max 0.8 2.15 3.0 -10 -10 3.25 0.03 24 4 12.5 Vil Vih Voh Vol 0.8 3.25 4.5 -10 -10 4.95 0.03 24 4 12.5 Unit V V V V A A mA mA mA V V V V A A mA mA mA
DVdd = 3.3V Low level input voltage High level input voltage High level output voltage Low level output voltage Input Leakage Current (AC-link inputs) Output Leakage Current (Tri-stated AC-link outputs) Output buffer drive current BIT_CLK SDATA_IN, EAPD S/PDIF_OUT (Note 5) DVdd = 5.0 V Low level input voltage High level input voltage High level output voltage Low level output voltage Input Leakage Current (AC-link inputs) Output Leakage Current (Tri-stated AC-link outputs) Output buffer drive current BIT_CLK SDATA_IN, EAPD S/PDIF_OUT (Note 5)
.35 10 10
.35 10 10
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SERIAL PORT TIMING
Parameter RESET# Timing Vdd stable to RESET# inactive RESET# active low pulse width RESET# inactive to BIT_CLK start-up delay 1st SYNC active to CODEC READY set Clocks BIT_CLK frequency BIT_CLK period BIT_CLK output jitter (depends on XTAL_IN source) BIT_CLK high pulse width BIT_CLK low pulse width SYNC frequency SYNC period SYNC high pulse width SYNC low pulse width Data Setup and Hold Output Propagation delay from rising edge of BIT_CLK Input setup time from falling edge of BIT_CLK Input hold time from falling edge of BIT_CLK Input Signal rise time Input Signal fall time Output Signal rise time (Note 5, 7) Output Signal fall time (Note 5, 7) Misc. Timing Parameters End of Slot 2 to BIT_CLK, SDATA_IN low (PR4) SYNC pulse width (PR4) Warm Reset SYNC inactive (PR4) to BIT_CLK start-up delay Setup to trailing edge of RESET# (test mode) (Note 5) Rising edge of RESET# to Hi-Z delay (Note 5) Symbol Tvdd2rst# Trst_low Trst2clk Tsync2crd Fclk Tclk_period Tclk_high Tclk_low Fsync Tsync_period Tsync_high Tsync_low Tco Tisetup Tihold Tirise Tifall Torise Tofall Ts2_pdown Tsync_pr4 Tsync2clk Tsetup2rst Toff Min 5 1.0 25 36 36 10 0 2 2 2 2 1.1 162.8 15 Typ . 120 62.4 12.288 81.4 40.7 40.7 48 20.8 1.3 19.5 6 4 4 .34 350 Max Unit ms s s s MHz ns ps ns ns kHz s s s ns ns ns ns ns ns ns s s ns ns ns
750 45 45 12 6 6 6 6 1.0 25
Notes: 7. BIT_CLK measured with 47 series termination and CL = 50 pF.
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BIT_CLK Trst_low RESET# Tvdd2rst# Vdd Trst2clk
Figure 1. Power Up Timing
BIT_CLK
SYNC Tsync2crd CODEC_READY
Figure 2. Clocks
BIT_CLK Torise SYNC Tirise Tsync_high Tifall Tsync_low Tclk_high Tclk_low Tclk_period Tifall
Tsync_period
Figure 3. Codec Ready from Startup or Fault Condition
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BIT_CLK
SDATA_IN Tco SDATA_OUT, SYNC
Tisetup
Tihold
Figure 4. Data Setup and Hold
BIT_CLK Slot 1 SDATA_OUT Write to 0x20 Slot 2 Data PR4 Ts2_pdown SDATA_IN Don't Care
SYNC Tsync_pr4 T sync2clk
Figure 5. PR4 Powerdown
RESET# Tsetup2rst SDATA_OUT, SYNC SDATA_IN, BIT_CLK
Toff Hi-Z
Figure 6. Test Mode
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CS4298
2. GENERAL DESCRIPTION
2.1 Overview The CS4298 is a Mixed-Signal Audio/Modem Codec (AMC) based on the AC `97 1.0 Specification, and the AC `97 2.0 Extensions. It is designed to be paired with a digital controller, typically located on the PCI bus. The AMC Controller is responsible for all communications between the CS4298 and the rest of the system. The CS4298 functions as an analog mixer, a stereo audio ADC, a stereo audio DAC, a dual modem AFE, and a control and digital stream interface to the AMC Controller. The CS4298 contains three distinct functional sections: Digital, Analog Audio, and Analog Modem. The Digital Section includes the AC-Link registers, power management support, SYNC detection circuitry, and AC-Link serial port interface logic. The Analog Audio section includes the analog input multiplexor (mux), stereo output mixer, stereo ADCs, stereo DACs, and analog volume controls. The Analog Modem section includes dual differential ADCs, dual differential DACs, analog loopback logic, GPIO control and status, and power down and wake-up logic. 2.2 Modes of Operation The CS4298 has four basic modes of operation. Each mode allows varying functionality to meet a wide variety of software and hardware configurations. On power up or system reset, the device reverts to the basic configuration Mode 0. The audio ADC's and DAC's functionality remains fixed for each mode, but the modem ADC's and DAC's functionality changes per each configuration. From a system perspective, the device can provide standard audio with modem, two line interface, speakerphone, and four channel enhanced audio.
2.2.1
Mode 0
This is the default operating mode for the CS4298. It supports the legacy AC `97 audio modes of operation including audio mixer, ADC's, and DAC's. The modem configuration supports a phone line for modem ADC/DAC1 and a handset interface for modem ADC/DAC2.
2.2.2
Mode 1
This is the two phone line mode of operation. It is similar to mode 0 but the modem ADC/DAC2 is interfaced to a second phone line in place of the handset.
2.2.3
Mode 2
This mode facilitates a full duplex speakerphone mode of operation. The ADC of modem ADC/DAC2 is connected directly to the audio microphone in place of the handset or line 2 input. This dedicated microphone capture path allows the host controller to implement echo cancellation for hands free telephone operation. The modem DAC2 is not used in this mode.
2.2.4
Mode 3
Mode 3 is the four channel expansion mode. The modem ADC/DAC pairs are utilized for enhanced audio functionality. The modem DAC's are routed to the alternate line audio outputs providing 2 additional audio channels. The modem ADC inputs may be connected to the output of the analog stereo input mixer for enhanced audio effect processing or enhanced digital docking in a note book application.
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3. DIGITAL SECTION
3.1 AC-Link All communication with the Codec is estabDigital AC'97 lished with a 5-wire digital interface to the ConCODEC SYNC Controller troller chip as shown in Figure 7. All clocking for the serial communication is synchronous to BIT_CLK the BIT_CLK signal. BIT_CLK is generated by the primary Codec and is used to slave the ConSDATA_OUT troller and any secondary Codecs, if applicable. An AC-link audio frame is a sequence of 256 seSDATA_IN rial bits organized into 13 groups referred to as RESET# `slots'. One frame consists of one 16-bit slot and twelve 20-bit slots. During each audio frame, data is passed bi-directionally between the CoFigure 7. AC-link Connections dec and the Controller. The input frame is driven from the Codec on the SDATA_IN line. The output frame is driven from the Controller SDATA_OUT line. Both input and output frames contain the same number of bits and are organized with the same `slot' configuration. The input and output frame have differing functions for each slot. The Controller synchronizes the beginning of a frame with the SYNC signal. In Figure 9 the position of each bit location within the frame is noted. The first bit position in a new serial data frame is F0 and the last bit position in the serial data frame is F255. When SYNC goes active (high) and is sampled active by the CS4298 (on the falling edge of BIT_CLK), both devices are synchronized to a new serial data frame. The data on the SDATA_OUT pin at this clock edge is the final bit of the previous frame's serial data. On the next rising edge of BIT_CLK, the first bit of Slot 0 is driven by the Controller on the SDATA_OUT pin. The CS4298 latches in this data, as the first bit of the frame, on the next falling edge of the BIT_CLK clock signal. The Controller is also responsible for issuing reset via the RESET# signal. After being reset, the Codec is responsible for flagging the Controller that it is ready for operation after synchronizing its internal functions. The AC-link signals may be referenced to either 5 Volts or 3.3 Volts. The CS4298 must use the same digital supply voltage as the Controller chip. 3.2 Control registers All read accesses to the Codec are generated by requesting a register address (index number) in slot 1 of a SDATA_OUT frame. The following SDATA_IN frame will contain the register content in its slot 2. The write operation is identical with the index in slot 1 and the write data in slot 2. The AC `97 Frame Definition section details the function of each input and output frame. Individual register descriptions are found in the Register Interface section. AC-97 Register Interface The CS4298 implements the AC '97 Registers in accordance with the AC '97 2.0 Specification. See the Register Interface section for details on the CS4298's register set.
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4. ANALOG SECTION
Please refer to Figure 8, Mixer diagram, for a high-level graphical representation of the CS4298 analog mixer structure. 4.1 Audio Output Mixer There are two output mixers on the CS4298. The stereo output mixer sums together the analog outputs from the Input Mixer, 3D enhancement, and the PCM DAC output. The stereo output mix is sent to the LINE_OUT and ALT_LINE_OUT output pins of the CS4298. When the device is set to Mode 3 or Mode 0-2 and the EAM in AC Mode Control (Index 5Eh) is set, the modem DAC outputs are routed to ALT_LINE_OUT. Audio Input Mux The input multiplexor controls which analog input is sent to the ADCs. The output of the input mux is converted to stereo 18-bit digital PCM data and sent to the AMC Controller chip in Slots 3 and 4 of the AC-Link SDATA_IN signal. Audio Input Mixer The input mixer is an analog mix of the analog input signals such as MIC, LINE_IN, etc., and the PCM Audio DAC output. The output of the mixer is routed to the ADC Input Mux, Audio Output Mixer, and may be routed to the Modem ADC input. Audio Volume Control The volume control registers of the AC '97 Register interface control analog input level to the input mixer, the master volume level, and the alternate volume level. All analog volume controls implement volume steps at nominally 1.5 dB per step. The analog inputs allow a mixing range of +12 dB of signal gain to -34.5 dB of signal attenuation. The analog output volume controls allows from 0 dB to -94.5 dB of attenuation.
4.2
4.3
4.4
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MAIN D/A CONVERTERS PCM_OUT MIC1 MIC2 LINE 2 / 2 / VOL MIC SELECT +20dB VOL DAC VOL
2 / PCM OUT PATH MUTE
MUTE STEREO INPUT MIXER
3D
MASTER VOLUME OUTPUT BUFFER 2
MUTE
STEREO OUTPUT MIXER
VOL
/
LINE_OUT
CD
VOL
MUTE
VIDEO
2 /
VOL
MUTE
ALTERNATE VOLUME VOL STEREO TO MONO MIXER 2 / OUTPUT BUFFER 2 / ALT_LINE_OUT
AUX
2 /
VOL
MUTE
VOL
MUTE
MAIN ADC GAIN ADC INPUT MUX VOL MUTE ADC
SDATA_OUT RESET# SYNC Mode Control MRX+ (loopback) MTX+ MRX(loopback) MTXVref HRX+ (loopback) HTX+ VOL ADC HRX(loopback) HTXVref VOL HRXDAC VOL ADC VOL MRX+ HRX+ -+ Class AB Dif out +DAC
SDATA_IN
AC-Link Interface
3 / MRX-+ Class AB Dif out +-
BIT_CLK 10 / GPIO
MTX+
MTX-
HTX+
HTX-
Figure 8. Mixer Diagram
DS315PP2
15
CS4298
5. AC `97
5.1 AC `97 Frame Definition The AC Link is a bi-directional serial port with thirteen time-division multiplexed slots in each direction. The first slot is 16 bits long and termed the tag slot. Bits in the tag slot determine if the Codec is ready and indicate which, if any, other slots contain valid data. Slots 1 through 11 are 20-bits long and can contain audio data. Slot 12 contains data to be written and read from GPIO. The serial data line is defined from the Controller's perspective, NOT from the Audio Codec's perspective. AC-Link Serial Data Output Frame In the serial data output frame, data is passed on the SDATA_OUT pin TO the CS4298 FROM the Controller. Figure 9 illustrates the serial port timing.
5.2
20.8 S (48 kHz) Tag Phase SYNC 12.288 MHz 81.4 nS BIT_CLK Data Phase
Bit Frame Position: F255
F0 Valid Frame
F1 Slot 1 Valid
F2 Slot 2 Valid
F12
F13
F14
F15
F16
F35
F36
F56
F57
F76
F97
F255
SDATA_OUT
X
0
0
SCRA1 SCRA0
R/W
0
WD15
LP19
LP18
RP19
X
X
Bit Frame Position: F255
F0 Codec Ready
F1 Slot 1 Valid
F2 Slot 2 Valid
F12
F13
F14
F15
F16
F35
F36
F56
F57
F76
F97
F255
SDATA_IN
0
0
0
0
0
0
0
RD15
LC17
LC16
RC17
0
0
Slot 0
Slot 1
Slot 2
Slot 3
Slot 4
Slots 5-12
Figure 9. AC-link Input and Output Framing
16
DS315PP2
CS4298
5.3 5.3.1
Bit 15
AC-Link AudioOutput Frame Serial Data Output Slot Tags (Slot 0)
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Valid Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8 Slot 9 Slot 10 Slot 11 Slot 12 Frame Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid
SCRA SCRA 1 0
Valid FrameDetermines if any of the following slots contain either valid playback data for the Codec's DACs, data for read/write operation, or GPIO data. When set, at least one of the other AC-link slots contain valid data. If this bit is clear, the remainder of the frame is ignored. Slot [1:2] ValidIndicates valid slot data when accessing the register set of the primary Codec (SCRA[1:0] = 00). For a read operation, Slot 1 Valid is set when Register Address (Slot 1) contains valid data. For a write operation, Slot 1 Valid and Slot 2 Valid are set indicating Register Address (Slot 1) and Register Write Data (Slot 2) contain valid data. The register address and write data must be valid within the same frame. SCRA[1:0] must be cleared when accessing the primary Codec. The physical address of a Codec is determined by the ID[1:0]# input pins which are reflected in the Extended Audio ID (Index 28h) register and the Extended Modem ID (Index 3Ch) register. Slot [3:11] Valid If a Slot Valid bit is set, the named slot contains valid audio data. If the bit is clear, the slot will be ignored. The definition of each slot is determined by the basic operating mode selected for the CS4298. For more information, see the AC Mode Control (Index 5Eh) register. Slot 12 ValidIf Slot 12 Valid is set, Slot 12 contains valid write data for the GPIO pins. SCRA[1:0] Secondary Codec Register Access. Unlike the primary Codec, SCRA[1:0] indicate valid slot data when accessing the register set of a secondary Codec. The value set in SCRA[1:0] (01,10,11) determines which of the three possible secondary Codecs is accessed. For a read operation, the SCRA[1:0] bits are set when Register Address (Slot 1) contains valid data. For a write operation, SCRA[1:0] bits are set when Register Address (Slot 1) and Register Write Data (Slot 2) contain valid data. The write operation requires the register address and the write data to be valid within the same frame. SCRA[1:0] must be cleared when accessing the primary Codec. They must also be cleared during the idle period where no register read or write is pending. The physical address of a Codec is determined by the ID[1:0]# input pins which are reflected in the Extended Audio ID (Index 28h) register and the Extended Modem ID (Index 3Ch) register. The SCRA[1:0] bits are listed as the ID[1:0] bits in Slot 0 in the AC `97 specification.
5.3.2
Bit 19
Register Address (Slot 1)
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R/W# RI6
RI5
RI4
RI3
RI2
RI1
RI0
R/W #
RI[6:0]
Read/Write#. Determines if a read (R/W# = 1) or write (R/W# = 0) operation is requested. For a read operation, the following Input Frame will return the register index in the Read-Back Address Port (Slot 1) and the contents of the register in the Read-Back Data Port (Slot 2). A write operation does not return any valid data in the following frame. If the R/W# bit = 0, data must be valid in both the Register Address (Slot 1) and the Register Write Data (Slot 2) during a frame when Slot [1:2] Valid or SCRA[1:0] are set. Register index/address. Registers can only be accessed on word boundaries; RI0 must be set to 0. RI[6:0] must contain valid data during a frame when the Slot 1 Valid or SCRA[1:0] are set.
DS315PP2
17
CS4298
5.3.3
Bit 19
Register Write Data (Slot 2)
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WD15 WD14 WD13 WD12 WD11 WD10 WD9 WD8 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0
WD[15:0]
Codec register data for write operations. For read operations, this data is ignored. If R/W# = 0, data must be valid in both the Register Address (Slot 1) and the Register Write Data (Slot 2) during a frame when the Slot [1:2] Valid = 11 or either SCRA[1:0] bit is set. Splitting the register address and the write data across multiple frames is not permitted.
5.3.4
Bit 19
Playback Data (Slots 3-11)
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
PD[19:0]
20-bit PCM playback (2's compliment) data for the left and right DACs, S/PDIF transmitter, or GPIO pins. Any PCM data from the Controller less than 20 bits should be left justified in the slot and zeropadded. Table 9 on page 35 lists the definition of each respective slot. The mapping of a given slot is determined by the MD[1:0] bits found in the AC Mode Control (Index 5Eh) register.
5.3.5
Bit 19
GPIO Data (Slot12)
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GP9 GP8 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0
GP[9:0]
GPIO Output Date. Output data is transferred to the GPIO pins every frame in Slot 12.
5.4
AC-Link Audio Input Frame In the serial data input frame, data is passed on the SDATA_IN pin FROM the CS4298 to the AC '97 Controller. The data format for the input frame is very similar to the output frame. Figure 9 illustrates the serial port timing. Serial Data Input Slot Tag Bits (Slot 0)
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
5.4.1
Bit 15
Codec Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8 Slot 9 Slot 10 Slot 11 Slot 12 Ready Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid
Codec ReadyIndicates the readiness of the CS4298's AC-link and Control and Status registers. Immediately after a Cold Reset this bit will be clear. Once the CS4298's clocks and voltages are stable, this bit will be set. Until the Codec Ready bit is set, no AC-link transactions should be attempted by the Controller. The Codec Ready bit does not indicate readiness of the DACs, ADCs, Vref, or any other analog function. Those must be checked in the Power Down Control/Status (Index 26h), Ext'd Audio Ctrl/Stat (Index 2Ah), and Ext'd Modem Ctrl/Stat (Index 3Eh) registers by the Controller before any access is made to the mixer registers. Any accesses to the Codec while Codec Ready is clear is ignored. Slot 1 Valid Tag Indicates Slot 1 contains a valid read back address. Slot 2 Valid Tag Indicates Slot 2 contains valid register read data. Slot [3:11] Valid Tag Indicates Slot [3:11] contains valid capture data from the Codec's ADC. Slot 12 Valid Tag Indicates Slot 12 contains valid read data of the GPIO Pin Status Register (Index 54h).
18
DS315PP2
CS4298
5.4.2
Bit 19
Read-Back Address Port (Slot 1)
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RI6
RI5
RI4
RI3
RI2
RI1
RI0
RI[6:0]
Register index. The Read-Back Address Port echoes the AC '97 Register address when a register read has been requested in the previous frame. The Codec will only echo the register index for a read access. Write accesses will not return valid data in Slot 1.
5.4.3
Bit 19
Read-Back Data Port (Slot 2)
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
RD[15:0]
16-bit register value. The Read-Back Data Port contains the register data requested by the Controller from the previous read request. All read requests will return the read address in the Read-Back Address Port (Slot 1) and the register data in the Read-Back Data Port (Slot 2) on the following serial data frame.
5.4.4
Bit 19
PCM Capture Data (Slot 3-11)
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CD17 CD16 CD15 CD14 CD13 CD12 CD11 CD10 CD9 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0
CD[17:0]
18-bit PCM (2's compliment) data. The mapping of a given slot to an ADC is determined by the state of the MD[1:0] bits found in the AC Mode Control (Index 5Eh) register.
5.4.5
Bit 19
GPIO Pin Status (Slot 12)
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GI9
GI8
GI7
GI6
GI5
GI4
GI3
GI2
GI1
GI0
IRQ
GI[9:0] IRQ
Status of the GPIO[9:0] pin. Set when the GPIO generates a wake up or interrupt cycle. See GPIO Pin Wake Up Mask (Index 52h) register.
The capture data in Slot [3:12] will only be valid when the respective slot valid bit is set in Slot 0.
DS315PP2
19
CS4298
5.5 AC '97 Reset Modes Three methods of resetting the CS4298, as defined in the AC '97 Specification, are supported: Cold AC '97 Reset, Warm AC '97 Reset, and AC '97 Register Reset. A Cold AC '97 Reset is required to restart the AC-link when bit PR5 is set in the Power Down Control/Status (Index 26h) register.
5.5.1
Cold AC `97 Reset
A Cold Reset is performed by asserting RESET# in accordance with the minimum timing specifications in the Serial Port Timing section. Once de-asserted, all of the Codec's registers will be reset to their default power-on states and the BIT_CLK clock and SDATA_IN signals will be reactivated. The timing of power-up/reset events is discussed in detail in the Power Management section.
5.5.2
Warm AC '97 Reset
The CS4298 may also be reactivated when the AC-link is powered down (refer to the PR4 bit description in the Power Management section) by a Warm Reset. A Warm Reset allows the AC-link to be reactivated without losing information in the Codec's registers. Warm Reset is initiated when the SYNC signal is driven high for at least 1 s and then driven low in the absence of the BIT_CLK clock signal. The BIT_CLK clock will not restart until at least 2 normal BIT_CLK clock periods ( 162.8 ns) after the SYNC signal is de-asserted.
5.5.3
AC '97 Register Reset
The third reset mode provides a register reset to the CS4298. This is available only when the CS4298's AC-link is active and the Codec Ready bit is set. The audio and modem subsections may be reset independently. Any write to Reset (Index 00h) register will reset the audio subsection while any write to Ext'd Modem Ctrl/Stat (Index 3Eh) register will reset the modem subsection. See the respective register descriptions for additional information.
5.6
AC-Link Protocol Violation - Loss of SYNC The CS4298 is designed to handle SYNC protocol violations. The following are situations where the SYNC protocol has been violated: * The SYNC signal is not sampled high for exactly 16 BIT_CLK clock cycles at the start of an audio frame. * The SYNC signal is not sampled high on the 256th BIT_CLK clock period after the previous SYNC assertion. * The SYNC signal goes active high before the 256th BIT_CLK clock period after the previous SYNC assertion. Upon loss of synchronization with the Controller, the Codec will mute all analog outputs and clear the Codec Ready bit in the serial data input frame until two valid frames are detected. During this detection period, the Codec will ignore all register reads and writes and will discontinue the transmission of PCM capture data.
20
DS315PP2
CS4298
6. REGISTER INTERFACE
Certain register locations change definition based on the basic operating mode (Mode 0-3) selected by the MD[1:0] bits found in the AC Mode Control (Index 5Eh) register. The reset default is Mode 0.
Reg Num
00h 00h 00h 00h 02h 04h 06h 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 1E 20h 22h 26h 28h 28h 28h 28h 2Ah 2Ah 2Ah 2Ah 2Ch 2Eh 30h 32h 34h 36h 38h 3Ch 3Ch 3Ch 3C 3E 3E 3E 3E 40 42 44 46 Reset Reset Reset Reset Master Volume Master Volume Mono Mic Volume Line In Volume CD Volume Video Volume Aux Volume PCM Out Vol Record Select Record Gain Record Gain Microphone General Purpose 3D Control Powerdown Ctrl/Stat Ext'd Audio ID Mode 0 Ext'd Audio ID Mode 1 Ext'd Audio ID Mode 2 Ext'd Audio ID Mode 3 Ext'd Audio Ctrl Mode 0 Ext'd Audio Ctrl Mode 1 Ext'd Audio Ctrl Mode 2 Ext'd Audio Ctrl Mode 3 PCM Front DAC Rate PCM LFE DAC Rate MIC ADC Rate Center LFE Volume LR Surround Volume Ext'd Modem ID Mode 0 Ext'd Modem ID Mode 1 Ext'd Modem ID Mode 2 Ext'd Modem ID Mode 3 PRL PRK PRJ PRI MADC LDAC SDAC CDAC SR8 SR8 SR8 SR8 SR8 SR7 SR7 SR7 SR7 SR7 SR6 SR6 SR6 SR6 SR6 SR5 SR5 SR5 SR5 SR5 SR4 SR4 SR4 SR4 SR4 SR3 SR3 SR3 SR3 SR3 SR2 SR2 SR2 SR2 SR2 SR1 SR1 SR1 SR1 SR1 SR0 SR0 SR0 SR0 SR0 ID1 ID1 ID1 ID1 PR6 ID0 ID0 ID0 ID0 LDAC SDAC CDAC PR5 PR4 PR3 PR2 PR1 PR0 Mute Mute POP 3D MS LPBK S3 REF S2 ANL S1 DAC S0 ADC VRA VRA VRA VRA GL3
Name
Mode 0 Mode 1 Mode 2 Mode 3
D15
D14 D13 D12
D11
D10
D9 0 0 0 0
D8 ID8 ID8 ID8 ID8
ML0 ML0
D7 ID7 ID7 ID7 ID7
D6
D5
D4 ID4 ID4 ID4 0
D3 0 0 0 0
MR3 MR3 MM3 GN3 GR3 GR3 GR3 GR3 GR3 GR3 GR3
D2 0 0 0 0
MR2 MR2 MM2 GN2 GR2 GR2 GR2 GR2 GR2 SR2 GR2 GR2
D1 0 0 0 0
MR1 MR1 MM1 GN1 GR1 GR1 GR1 GR1 GR1 SR1 GR1 GR1
D0 0 0 0
MR0 MR0 MM0 GN0 GR0 GR0 GR0 GR0 GR0 SR0 GR0 GR0
Default
1990h 1990h
SE4 SE3 SE2 SE1 SE4 SE3 SE2 SE1 SE4 SE3 SE2 SE1 SE4 SE3 SE2 SE1
Mute Mute Mute Mute Mute Mute Mute Mute GL4 GL4 GL4 GL4 GL4 GL3 GL3 GL3 GL3 GL3 GL2 GL2 GL2 GL2 GL2 SL2 GL2 ML5 ML5 ML4 ML4 ML3 ML3 ML2 ML2
ID0 1991h
1980h 8000h 8000h 8000h 8008h 8808h 8808h 8808h 8808h 8808h 0000h 8000h 8000h 0000h 0000h 000Fh x000h x000h x000h x1C0h 0000h 0000h 0200h 01C0h BB80h BB80h BB80h BB80h BB80h
ML1 ML1
MR5 MR5 20dB
MR4 MR4 MM4 GN4 GR4 GR4 GR4 GR4 GR4
Alternate Line Out Volume Mute
GL1 GL1 GL1 GL1 GL1 SL1 GL1
GL0 GL0 GL0 GL0 GL0 SL0 GL0
SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR15 SR14 SR13 SR12 SR11 SR10 SR9 Mute Mute ID1 ID1 ID1 ID1 ID0 ID0 ID0 ID0 PRG PRF PRE PRD PRD PRD PRG PRC PRC PRC PRC PRB PRB PRB PRB LFE5 LFE4 LFE3 LFE2 LFE1 LSR5 LSR4 LSR3 LSR2 LSR1
PCM Surround DAC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9 PCM Left/Right ADC Rate SR15 SR14 SR13 SR12 SR11 SR10 SR9
LFE0 Mute LSR0 Mute
CNT5 CNT4 CNT3 CNT2 CNT1 RSR5 RSR4 RSR3 RSR2 RSR1 HSET LIN2
CNT0 8080h RSR0 8080h LIN1 LIN1 x005h x003h x001h x000h
Ext'd Modem Stat/Ctrl PRH Mode 0 Ext'd Modem Stat/Ctr Mode1 Ext'd Modem Stat/Ctrl PRH Mode 2 Ext'd Modem Stat/Ctrl Mode 3 Line 1 DAC/ADC Rate Line 2 DAC/ADC Rate Handset DAC/ADC Rate Line 1 DAC/ADC Level
PRA PRA PRA PRA SR8 SR8 SR8
HDAC HADC
DAC1 ADC1 MREF GPIO 00CFh DAC2 ADC2 DAC1 ADC1 MREF GPIO 003Fh
HDAC HADC SR7 SR7 SR7 SR6 SR6 SR6 SR5 SR5 SR5 SR4 SR4 SR4
DAC1 ADC1 MREF GPIO 008Fh ADC1 MREF GPIO 0047h SR3 SR3 SR3 SR2 SR2 SR2 SR1 SR1 SR1 SR0 SR0 SR0 BB80h BB80h BB80h 8080h
SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR15 SR14 SR13 SR12 SR11 SR10 SR9 SR15 SR14 SR13 SR12 SR11 SR10 SR9 Mute
DAC3 DAC2 DAC1 DAC0 Mute
ADC3 ADC2
Table 1. Mixer Registers
DS315PP2
21
CS4298
Reg Num
48 4A 4C 4E 50 52 54 56 56 56 56
Name
Line 2 DAC/ACD Level Handset DAC/ACD Level GPIO Pin Configuration GPIO Pin Polarity/Type GPIO Pin Sticky GPIO Pin Walk-up Mask GPIO Pin Status Misc. Modem AFE Stat Mode 0 Misc. Modem AFE Stat Mode 1 Misc. Modem AFE Stat Mode 2 Misc. Modem AFE Stat Mode 3 Crystal Revision / Fab Slot Map Register S/PDIF Enable Vendor ID1(CR) Vendor ID2(Y-)
D15
Mute Mute
D14 D13 D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
8080h 8080h
DAC3 DAC2 DAC1 DAC0 Mute DAC3 DAC2 DAC1 DAC0 Mute GC9 GP9 GS9 GW9 GI9 GC8 GP8 GS8 GW8 Gi8 GC7 GP7 GS7 GW7 GI7 GC6 GP6 GS6 GW6 GI6 GC5 GP5 GS5 GW5 GI5 GC4 GP4 GS4 GW4 GI4
ADC3 ADC2 ADC3 ADC2 GC3 GP3 GS3 GI3 GC2 GP2 GS2 GI2 GC1 GP1 GS1 GW1 GI1 GC0 GP0 GS0 GI0
03FFh FFFFh 0000h xxxxh
GW3 GW2
GW0 0000h
HSB2 HSB1 HSB0 L2B2 L2B1 L2B0
L1B2 L1B1 L1B2 L1B1 L1B2 L1B1
L1B0 0000h L1B0 0000h L1B0 0000h 0000h
Cirrus Defined Registers: 5A 5E 68 7Ch 7Eh 1 EDM SPEN F7 T7 EAM 1 DDM 1 MD1 0 MD0 S0 0302h 0000h 4352h
V
F6 T6 F5 T5
Fs
F4 T4
L
F3 T3
CC6
F4 T2
CC5
F1 T1
CC4 CC3
F0 T0 S7
CC2 CC1 CC0
S6 PID2 S5 PID1 S4 PID0
Pre
S3
Copy #Audio S2 RID2 S1 RID1
Pro 0000h
RID0 5923h
Table 1. Mixer Registers (cont.)
22
DS315PP2
CS4298
6.1 6.1.1
Mode
Register Descriptions Reset (Index 00h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 1 2 3
SE4 SE4 SE4 SE4
SE3 SE3 SE3 SE3
SE2 SE2 SE2 SE2
SE1 SE1 SE1 SE1
SE0 SE0 SE0 SE0
0 0 0 0
ID8 ID8 ID8 ID8
ID7 ID7 ID7 ID7
0 0 0 0
0 0 0 0
ID4 ID4 ID4 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 ID0 0
SE[4:0] ID8 set ID7 set ID4 set ID1 set
3D Stereo Enhancement Technique. 00110 - Crystal 3D Stereo Enhancement. 18-bit ADC resolution. 20-bit DAC resolution. Headphone out support. (Alternate Line Output) Dedicated Mic PCM.
Read-only dataMode 0,1 1990h Mode 2 1991h Mode 3 1980h
Any write to this register causes the audio control registers (Index 02h - 38h) and the Crystal specific registers (Index 5Eh - 68h) to be reset forcing them to their default state. The mode control bits MD[1:0] of the AC Mode Control (Index 5Eh) register are also cleared forcing the Codec to Mode 0 configuration. Reads return configuration information about the audio Codec 6.1.2
D15
Master Volume (Index 02h)
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Mute
ML5
ML4
ML3
ML2
ML1
ML0
MR5
MR4
MR3
MR2
MR1
MR0
Mute ML[5:0] MR[5:0] Default
Master mute for the LINE_OUT_L and the LINE_OUT_R output signals. Master Volume control for LINE_OUT_L pin. Least significant bit represents -1.5 dB with 00000 = 0 dB. The total range is 0 dB to -94.5 dB. Master Volume control for LINE_OUT_R pin. Least significant bit represents -1.5 dB with 00000 = 0 dB. The total range is 0 dB to -94.5 dB. 8000h, corresponding to 0 dB attenuation and mute on.
In Mode 3 the LINE_OUT volume is controlled by the Left Right Surround (Index 38h) register in place of Master Volume.
DS315PP2
23
CS4298
6.1.3
D15
Alternate Volume (Index 04h)
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Mute
ML5
ML4
ML3
ML2
ML1
ML0
MR5
MR4
MR3
MR2
MR1
MR0
Mute ML[5:0] MR[5:0] Default
Master mute for the ALT_LINE_OUT_L and the ALT_LINE_OUT_R output signals. Master Volume control for ALT_LINE_OUT_L pin. Least significant bit represents -1.5 dB with 00000 = 0 dB. The total range is 0 dB to -94.5 dB. Master Volume control for ALT_LINE_OUT_R pin. Least significant bit represents -1.5 dB with 00000 = 0 dB. The total range is 0 dB to -94.5 dB. 8000h, corresponding to 0 dB attenuation and mute on.
In Mode 3 the ALT_LINE_OUT volume is controlled by the LFE/CNT Volume (Index 36h) register in place of Alternate Volume..
ML[5:0]/MR[5:0]/MM[5:0] Write 000000 000001 ... 111111 ML[5:0]/MR[5:0]/MM[5:0 Read 000000 000001 ... 111111 Gain Level 0 dB -1.5 dB ... -94.5 dB
Table 2. Alternate Line-Out and Master Mono Attenuation
6.1.4
D15
Microphone Volume (Index 0Eh)
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Mute
20dB
GN4
GN3
GN2
GN1
GN0
Mute GN[4:0] 20dB Default
When set, mutes MIC1/MIC2 signal. MIC1/MIC2 Volume Control. Least significant bit represents 1.5 dB with 01000 = 0 dB. The total range is 12 dB to -34.5 dB. Enables 20 dB microphone gain block. 8008h, 0 dB attenuation and Mute set.
This register controls the gain level of the Microphone input source to the Input Mixer. It also controls the +20 dB gain block which connects to the input volume control and to the Input Record Mux. The selection of MIC1 or MIC2 input pins is controlled by the MS bit in the General Purpose (Index 20h) register. The gain mapping for this register is shown in Table 3.
GN4 - GN0 00000 00001 ... 00111 01000 01001 ... 11111 Gain Level +12.0 dB +10.5 dB ... +1.5 dB 0.0 dB -1.5 dB ... -34.5 dB Mic Gain with 20dB = 1 +32.0 dB 30.5 dB ... 21.5 dB 20.0 dB 18.5 dB ... -14.5 dB
Table 3. Analog Mixer Input Gain Values
24
DS315PP2
CS4298
6.1.5
D15
Stereo Analog Mixer Input Gain (Index's 10h - 18h)
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Mute
GL4
GL3
GL2
GL1
GL0
GR4
GR3
GR2
GR1
GR0
Mute GL[4:0] GR[4:0] Default
When set mutes the respective input. Setting this bit mutes both right and left inputs. Left Volume Control. Least significant bit represents 1.5 dB with 01000 = 0 dB. The total range is 12 dB to -34.5 dB. See Table 3. Right Volume Control. Least significant bit represents 1.5 dB with 01000 = 0 dB. The total range is 12 dB to -34.5 dB. See Table 3. 8808h, 0 dB gain with Mute enabled.
These registers control the gain levels of the analog input sources to the Input Mixer. The analog inputs associated with registers 10h-18h are found in Table 4.
Register Index 10h 12h 14h 16h 18h Function Line IN Volume CD Volume Video Volume Aux Volume PCM Out Volume
Table 4. Stereo Volume Register Index
6.1.6
D15
Input Mux Select (Index 1Ah)
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SL2
SL1
SL0
SR2
SR1
SR0
SL[2:0] SR[2:0] Default
Left Channel ADC input source select. Right Channel ADC input source select. 0000h, MIC inputs selected for both channels.
When capturing PCM data, this register controls the input MUX for the ADCs. Table 5 below lists the possible values for each input.
Sx2 - Sx0 0 1 2 3 4 5 6 7 Record Source MIC CD Input Video Input AUX Input Line Input Stereo Mix Mono Mix Not Available
Table 5. Input Mux Selection
DS315PP2
25
CS4298
6.1.7
D15
Record Gain (Index 1Ch)
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Mute
GL3
GL2
GL1
GL0
GR3
GR2
GR1
GR0
Mute GL[3:0] GR[3:0] Default
When set, mutes the input to the ADCs. Left ADC gain. Least significant bit represents +1.5 dB with 0000 = 0 dB. The total range is 0 dB to +22.5 dB. Right ADC gain. Least significant bit represents +1.5 dB with 0000 = 0 dB. The total range is 0 dB to +22.5 dB. 8000h, 0 dB gain with Mute on.
6.1.8
D15
Record Gain Microphone (Index 1Eh)
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Mute
GM3
GM2
GM1
GM0
Mute GM[3:0] Default
When set, mutes the input to MADC2. Dedicated Microphone gain. Least significant bit represents +1.5 dB with 0000 = 0 dB. The total range is 0 dB to +22.5 dB. 8000h, 0 dB gain with Mute on.
This register is only available in Mode 2. 6.1.9
D15
General Purpose (Index 20h)
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
POP
3D
MS
LPBK
POP 3D MS LPBK Default
PCM Output Path. By default, the PCM output is mixed prior to the 3D enhancement. When set, the PCM output is mixed after the 3D enhancement. 3D Enable. If set, enables the CrystalClear 3D stereo enhancement. Microphone Select. Determines which of the two MIC inputs are passed to the mixer. When set, MIC2 input is selected; when clear MIC1 is selected. Loopback. If set, enables Analog ADC/DAC Loopback Mode. 0000h.
6.1.10 3D Control (Index 22h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
S3
S2
S1
S0
S[3:0]
Default
Spacial Enhancement Depth. Spacial Enhancement is enabled by the 3D bit in the General Purpose (Index 20h) register. 0000 - No spacial enhancement. 1111 - Full spacial enhancement. 0000h, no spacial enhancement added.
The Spacial Enhancements is not available on the ALT_LINE output when the codec is in Mode 3 or EAM is set. See the AC Mode Control (Index 5Eh) register for more detail.
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6.1.11 Power Down Control/Status (Index 26h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PR6
PR5
PR4
PR3
PR2
PR1
PR0
REF
ANL
DAC
ADC
PR6 PR5 PR4 PR3
PR2 PR1 PR0 REF ANL DAC ADC Default
When set, the alternate line-out buffer is powered down. When set, the internal master clock is disabled. The only way to recover from setting this bit is through a cold AC `97 reset (driving the RESET# signal active). When set, the AC link is powered down. The AC link can be restarted through a warm AC `97 reset using the SYNC signal, or a cold AC `97 reset using the RESET# signal (the primary codec only). When set, the analog mixer and voltage reference are powered down. When clearing this bit, the ANL, ADC, and DAC bits should be checked before writing any mixer registers. Because the reference voltage is shared with the modem subsection, it will not power down unless the PRB bit is also set in the Ext'd Modem Stat/Ctrl (Index 3Eh) register. When set, the analog mixer is powered down (the voltage reference is still active). When clearing this bit, the ANL bit should be checked before writing any mixer registers. When set, the DACs are powered down. When clearing this bit, the DAC bit should be checked before sending any data to the DACs. When set, the ADCs and the ADC input muxes are powered down. When clearing this bit, no valid data will be sent down the AC link until the ADC bit goes high. Voltage Reference Ready Status. When set, indicates the voltage reference is at a nominal level. Analog Ready Status. When set, the analog output mixer, input multiplexer, and volume controls are ready. When clear, no volume control registers should be written. DAC Ready Status. When set, the DACs are ready to receive data across the AC link. When clear, the DACs will not accept any valid data. ADC Ready Status. When set, the ADCs are ready to send data across the AC link. When clear, no data will be sent to the Controller. 0000h, all blocks are powered on. The lower four bits will eventually change as the Codec finishes an initialization and calibration sequence.
The PR[6:0] are power-down control for different sections of the Codec. The REF, ANL, DAC, and ADC bits are status bits which, when set, indicate that a particular section of the Codec is ready. After the Controller receives the Codec Ready bit in Slot 0, these status bits must be checked before writing to any mixer registers.
DS315PP2
27
CS4298
6.1.12 Extended Audio ID (Index 28h)
Mode D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 1 2 3
ID1 ID1 ID1 ID1
ID0 ID0 ID0 ID0
LDAC SDAC CDAC
VRA VRA VRA VRA
ID[1:0]
LDAC SDAC CDAC VRA
Codec configuration ID. Primary is 00; Secondary is 01,10,or 11. This is a reflection of the ID[1:0]# configuration pins. The state of the ID# pins are determined at power-up and are the inverse of the ID bits in this register. PCM LFA DAC. Indicates a LFE DAC is supported. PCM Surround DAC. Indicates a Surround DAC is supported. PCM Center DAC. Indicates a Center DAC is supported. Variable Rate Audio. This bit is clear indicating variable sample rates are not supported.
Read-only data Mode 0,1,2 x000h. Where x is determined by the state of ID[1:0] input pins. Mode 3 x1C0h.
6.1.13 Extended Audio Status / Control (Index 2Ah)
Mode D15
0 0 PRL 0
D14
0 0 0
D13
0 0 0
D12
0 0 0
D11
0 0 0 0
D10
0 0
D9
0 0 0
D8
0 0 0
D7
0 0 0
D6
D5
D4
D3
D2
D1
D0
0 1 2 3
MDAC 0
PRK
PRJ
PRI
LDAC
SDAC
CDAC
CDAC LDAC SDAC MADC PRI PRJ PRK PRL Default
PCM Center DAC Ready. When set, the Center DAC is ready. PCM LFE DAC Ready. When set, the LFE DAC is ready. PCM Surround DAC Ready. When set, the Surround DACs are ready. MIC ADC Ready. When Set, the dedicated Microphone ADC is ready. PCM Center DAC Disable. When set, the Center DAC is disabled. PCM Surround DAC Disable. When set, the Surround DAC is disabled. PCM LFE DAC Disable. When set, the LFE DAC is disabled. Dedicated Microphone ADC Disable. When set, the MIC ADC is disabled. Mode 0,1 Mode 2 Mode 3 0000h 0200h 01C0h
CDAC, LDAC, SDAC, and MADC are read only bits.
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6.1.14 PCM Front DAC Rate (Index 2Ch)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SR15
SR14
SR13
SR12
SR11
SR10
SR9
SR8
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
SR[15:0] Default
Front DAC Sample Rate. Read-only value BB80h, indicating 48 kHz sample rate.
6.1.15 PCM Surround DAC Rate (Index 2Eh)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SR15
SR14
SR13
SR12
SR11
SR10
SR9
SR8
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
SR[15:0] Default
Surround DAC Sample Rate. Read-only value BB80h, indicating 48 kHz sample rate.
6.1.16 PCM LFE DAC Rate (Index 30h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SR15
SR14
SR13
SR12
SR11
SR10
SR9
SR8
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
SR[15:0] Default
LFE DAC Sample Rate. Read-only value BB80h, indicating 48 kHz sample rate.
6.1.17 PCM LR ADC Rate (Index 32h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SR15
SR14
SR13
SR12
SR11
SR10
SR9
SR8
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
SR[15:0] Default
LR ADC Sample Rate. Read-only value BB80h, indicating 48 kHz sample rate.
6.1.18 PCM MIC ADC Rate (Index 34h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SR15
SR14
SR13
SR12
SR11
SR10
SR9
SR8
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
SR[15:0] Default
MIC ADC Sample Rate. Read-only value BB80h, indicating 48 kHz sample rate.
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CS4298
6.1.19 Center LFE Volume (Index 36h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Mute
LFE5
LFE4
LFE3
LFE2
LFE1
LFE0
Mute
CNT5 CNT4 CNT3 CNT2 CNT1 CNT0
LFE[5:0] CNT[5:0] Default
LFE Volume. Least significant bit represents -1.5 dB with 00000 = 0 dB. The total range is 0 dB to 94.5 dB. Center Volume.Least significant bit represents -1.5 dB with 00000 = 0 dB. The total range is 0 dB to 94.5 dB. 8080h, indicating mute with 0 dB attenuation. LFE[5:0]/LSR[5:0] CNT[5:0]/RSR[5:0] Write 000000 000001 ... 111111 LFE[5:0]/LSR[5:0] CNT[5:0]/RSR[5:0] Read 000000 000001 ... 111111 Table 6. 6 Channel Volume Attenuation Gain Level 0 dB -1.5 dB ... -94.5 dB
6.1.20 LR Surround Volume (Index 38h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Mute
LSR5
LSR4
LSR3
LSR2
LSR1
LSR0
Mute
RSR5 RSR4 RSR3 RSR2 RSR1 RSR0
LSR[5:0] RSR[5:0] Default
Left Surround Volume. Least significant bit represents -1.5 dB with 00000 = 0 dB. The total range is 0 dB to -94.5 dB. Right Surround Volume. Least significant bit represents -1.5 dB with 00000 = 0 dB. The total range is 0 dB to -94.5 dB. 8080h, indicating 0 dB attenuation.
6.1.21 Extended Modem ID (Index 3Ch)
Mode D15
ID1 ID1 ID1 ID1
D14
ID0 ID0 ID0 ID0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
HSET
D1
LIN2
D0
0 1 2 3
LIN1 LIN1
HSET LIN1 LIN2 ID[1:0]
Default
Handset. Indicates handset ADC/DAC is supported. Line 1. When set, indicates 1st line is supported. Line 2. When set, indicates 2nd line is supported. Codec configuration ID. Primary is 00; Secondary is 01,10,or 11. This is a reflection of the configuration pins. The state of the ID# pins are determined at power-up and are the inverse of the ID bits in this register. Mode 0 x005h Mode 1 x003h Mode 2 x001h Mode 3 x000h Where x is determined by the state of ID[1:0] input pins.
The Extended Modem ID is a read/write register that identifies the Codec's modem capabilities. This register reports the features available based on the basic operating mode determined by MD[1:0] of AC Mode (Index 5Eh) register. Writing any value to this location issues a reset to the modem registers (Index 3Ch-56h). Audio registers are not reset by a write to this location. NOTE: All GPIO registers (Index 46h-54h) are reset by any write to this location.
30 DS315PP2
CS4298
6.1.22 Extended Modem ID (Index 3Eh)
Mode D15 PRH 0 1 PRH 2 3 D14
PRG PRF PRG PRE
D13
D12
D11
PRD PRD PRD
D10
PRC PRC PRC PRC
D9
PRB PRB PRB PRB
D8
PRA PRA PRA PRA
D7
HDAC HDAC
D6
HADC
D5
DAC2
D4
ADC2
D3
DAC1 DAC1 DAC1
D2
ADC1 ADC1 ADC1 ADC1
D1
MREF MREF MREF MREF
D0
GPIO GPIO GPIO GPIO
HADC
PRH PRG PRF PRE PRD PRC PRB
PRA HDAC HADC DAC2 ADC2 DAC1 ADC1 MREF GPIO Default
Handset DAC. When set powers down the Handset DAC. Handset ADC. When set powers down the Handset ADC. Line 2 DAC. When set powers down the Line 2 DAC. Line 2 ADC. When set powers down the Line 2 ADC. Line 1 DAC. When set powers down the Line 1 DAC. Line 1 ADC. When set powers down the Line 1 ADC. Modem Reference. When set powers down the modem reference. The modem and audio share a common reference. The reference will not power down unless PR3 of the Power Down Ctrl/Stat (Index 26h) register is also set. GPIO. When set the GPIO pins are tri-state and powered down. Slot 12 is marked invalid if the AC-link is active. Handset DAC. When set indicates the Handset DAC is ready. Handset ADC. When set indicates the Handset ADC is ready. Line 2 DAC. When set indicates the Line 2 DAC is ready. Line 2 ADC. When set indicates the Line 2 ADC is ready. Line 1 DAC. When set indicates the Line 1 DAC is ready. Line 1 ADC. When set indicates the Line 1 ADC is ready. Modem Reference. When set indicates the modem reference is ready. GPIO. When set the GPIO pins are ready. Slot 12 is marked valid. Mode 0 Mode 1 Mode 2 Mode 3 x0CFh x03Fh x08Fh x047h Where x is determined by the state of ID[1:0] input pins.
PR[A:H] are read/write bits that provide power management of the modem AFE subsection. All remaining bits are read/only status indicating modem subsystems are ready for operation. After reset or issuing a change to the MD[1:0] of AC Mode (Index 5Eh) register, the respective status bits for that mode will be clear until the subsystem becomes ready. 6.1.23 Line 1 DAC/ADC Rate (Index 40h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SR15
SR14
SR13
SR12
SR11
SR10
SR9
SR8
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
SR[15:0] Default
Line 1 DAC/ADC Sample Rate. Read-only value BB80h, indicating 48 kHz sample rate.
6.1.24 Line 2 DAC/ADC Rate (Index 42h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SR15
SR14
SR13
SR12
SR11
SR10
SR9
SR8
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
SR[15:0] Default
Line 2 DAC/ADC Sample Rate. Read-only value BB80h, indicating 48 kHz sample rate.
DS315PP2
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CS4298
6.1.25 Handset DAC/ADC Rate (Index 44h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SR15
SR14
SR13
SR12
SR11
SR10
SR9
SR8
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
SR[15:0] Default
Handset DAC/ADC Sample Rate. Read-only value BB80h, indicating 48 kHz sample rate.
6.1.26 Line 1 DAC/ADC Level (Index 46h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Mute
DAC3 DAC2 DAC1 DAC0
Mute
ADC3 ADC2
Mute[D15] Mute. Mutes the input of Line 1 DAC. Mute[D7] Mute. Mutes the output of Line 1 ADC. DAC[3:0] Line 1 DAC attenuation. Least significant bit represents 1.5 dB with 00000 = 0 dB. The total range is 0 dB to -22.5 dB. ADC[3:2] Line 1 ADC gain. Least significant bit represents 6 dB with 00 = 0 dB. The total range is 0 dB to +18 dB. Default 8080h indicating mute with 0 dB attenuation or gain.
When EAM of the AC Mode Control (Index 5Eh) is set, the Line 1 DAC attenuation is controlled by ML[4:0] of the Alternate Volume (Index 04h) register. 6.1.27 Line 2 DAC/ADC Level (Index 48h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Mute
DAC3 DAC2 DAC1 DAC0
Mute
ADC3 ADC2
Mute[D15] Mute. Mutes the input of Line 2 DAC. Mute[D7] Mute. Mutes the output of Line 2 ADC. DAC[3:0] Line 2 DAC attenuation. Least significant bit represents 1.5 dB with 00000 = 0 dB. The total range is 0 dB to -22.5 dB. ADC[3:2] Line 2 ADC gain. Least significant bit represents 6 dB with 00 = 0 dB. The total range is 0 dB to +18 dB. Default 8080h indicating mute with 0 dB attenuation or gain.
When EAM of the AC Mode Control (Index 5Eh) is set, the Line 2 DAC attenuation is controlled by MR[4:0] of the Alternate Volume (Index 04h) register. 6.1.28 Handset DAC/ADC Level (Index 4Ah)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Mute
DAC3 DAC2 DAC1 DAC0
Mute
ADC3 ADC2
Mute[D15] Mute. Mutes the input of Handset DAC. Mute[D7] Mute. Mutes the output of Handset ADC. DAC[3:0] Handset1 DAC attenuation. Least significant bit represents 1.5 dB with 00000 = 0 dB. The total range is 0 dB to -22 dB. ADC[3:2] Handset ADC gain. Least significant bit represents 6 dB with 00 = 0 dB. The total range is 0 dB to +18 dB. Default 8080h indicating mute with 0 dB attenuation or gain.
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6.1.29 GPIO Pin Configuration (Index 4Ch)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
GC9
GC8
GC7
GC6
GC5
GC4
GC3
GC2
GC1
GC0
GC[9:0] Default
GPIO Pin Configuration. When set defines the corresponding GPIO pin as an input 03FFh
After a cold reset, power up, or modem register reset (see Extended Modem ID (Index 3Ch)) all GPIO pins are configured as inputs. 6.1.30 GPIO Pin Polarity/Type Configuration (Index 4Eh)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1
1
1
1
1
1
GP9
GP8
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0
GP[9:0] Default
GPIO Pin Configuration. The definition of GP[9:0] changes based on the pin defined as an input or an output by GC[9:0] of GPIO Pin Configuration (Index 4Ch). FFFFh
When the GPIO pin is defined as an input, its status is reported in the GPIO Pin Status (Index 54h) register as well as Slot 12.
GCx 0 0 1 1 GPx 0 1 0 1 Function Output Output Input Input CMOS drive Open drain Active Low Active High (default)
Table 7. GPIO Input/Output Configuration
6.1.31 GPIO Pin Sticky (Index 50h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
GS9
GS8
GS7
GS6
GS5
GS4
GS3
GS2
GS1
GS0
GS[9:0] Default
GPIO Pin Sticky. If set, the GPIO pin input is latched. 0000h
If a GPIO is defined as "sticky" the input requires a transition of the GPIO input pin to set the corresponding bit in Slot 12 and the GPIO Pin Status (Index 54h) register. When "sticky" is set the corresponding bit in GPIO Pin Polarity/Type Configuration (Index 4Ah) register determines which edge of the GPIO pin will set GI[x]. If GP[x] is set, a low to high transition sets the GI[x] bit. A high to low transition sets GI[x] if GP[x] is clear. Once set, writing a 0 to GI[x] will clear the "sticky" input.
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CS4298
6.1.32
D15
GPIO Pin Wakeup Mask (Index 4Ch)
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
GW9
GW8
GW7
GW6
GW5
GW4
GW3
GW2
GW1
GW0
GS[9:0] Default
Wake up mask. If set, allow the GPIO input to generate AC-LINK wake up protocol. 0000h
The CS4298 has the ability to generate a "wake up" cycle by a transition of a GPIO pin when the AC-Link has been powered down. If a mask bit is set, a one being set in the corresponding GPIO Pin Status (Index 54h) will initiate a wake up interrupt. Bit 0 of SDATA_IN Slot 12 will be set indicating a GPIO interrupt. GPIO pins must be defined as "input", "sticky", and the mask set to allow a GPIO interrupt. The GPIO interrupt is cleared by writing a 0 to the respective status bit in GPIO Pin Status (Index 54h) register. 6.1.33 GPIO Pin Status (Index 54h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
GI9
GI8
GI7
GI6
GI5
GI4
GI3
GI2
GI1
GI0
GI[9:0]
GPIO pin status. Reflects the state of all GPIO pins either input or output. If the GPIO pin is defined as an output, the respective bit reflects the state of SDATA_OUT Slot 12. If the GPIO pin is defined as an input, the register is reflected in SDATA_IN Slot 12. GPIO output pins cannot be accessed by Slot 1,2 register access, only by SDATA_OUT Slot 12.
6.1.34 Misc. Modem AFE Status (Index 56h)
Mode D15 D14 D13 D12 D11 D10
HSB2
D9
HSB1
D8
HSB0
D7
D6
L2B2
D5
L2B1
D4
L2B0
D3
D2
L1B2 L1B2 L1B2
D1
L1B1 L1B1 L1B1
D0
0 1 2 3
L1B0 L1B0 L1B0
HSB[2:0] L2B[2:0] L1B[2:0] Default
Handset Loopback. Line 2 Loopback. Line 1 Loopback. 0000h. Loop Back Mode HSB[2:0], L2B[2:0], L1B[2:0] 000 001 010 011 100 101 110-111 Function Disabled Digital Loop Back Local Analog Loop Back DAC to ADC 1-Bit data Loop Back Remote Analog Loop Back AC-Link Loop Back Not Used
Table 8. Misc. Modem Configuration
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6.1.35 AC Mode Control (Index 5Eh)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
EDM
EAM
DDM
MD1
MD0
DDM
EAM EDM
MD[1:0]
Default
DAC Direct Mode. This bit controls the source to the line and alternate line output drivers. When set, the Left and Right DAC directly drive the line and alternate line outputs by bypassing the audio mixer. When clear, the audio mixer is the source for the line and alternate line outputs. Extended Audio Mode. When set the output of MDAC2 and MDAC1 are mapped to the ALT_LINE OUTPUT. The MDAC volumes are set by the Alternate Line Volume (Index 04h) register when in this mode. Extended Docking Mode. When set the output of the analog input mixer is routed to the MADC1 and MADC2 inputs. This allows any analog input mix to be digitized and routed to a second AC `97 codec or allows the host controller to add effects processing to analog sources. Mode. Sets basic operating mode for the codec. This effects the mapping of the ADCs and DACs to ACLINK Slot locations. See the Mode of Operation subsection for additional detail. Table XXX below details the Slot mapping. 0000h
Mode
0 1 2
Definition
Basic 2 Line Speakerphone Extended 4 Channel
Audio DAC1
Left 3 Left 3 Left 3 Surrnd Left 7
Audio DAC2
Right 4 Right 4 Right 4 Surrnd Right 8
Audio ADC1
Left 3 Left 3 Left 3 Left 3
Audio ADC2
Right 4 Right 4 Right 4 Right 4
Modem DAC1
Line 1 5 Line 1 5 Line 1 5 Center 6
Modem DAC2
Handset 11 Line 2 10 Handset 11 LFE 9
Modem ADC1
Line 1 5 Line 1 5 Line 1 5 Line 1 5
Modem ADC2
Handset 11 Line 2 10 Mic 6 Handset 11
GPIO
12 12 12
3
12
Table 9. Slot Assignments
6.1.36 S/PDIF Control (Index 68h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SPEN
V
0
0
L
CC6
CC5
CC4
CC3
CC2
CC1
CC0
Pre
Copy #Audio
0
SPEN V L CC[6:0] Pre Copy #Audio Default
S/PDIF Enable. When set, Slot 6 and Slot 9 are mapped to the SPDIF_OUT pin. When in Mode 3 and SPEN set, data is not passed to Modem DAC1 and Modem DAC2. Validity Bit. When set, this bit notifies the S/PDIF receiver that the subframe data is not suitable for conversion. Generation Level. Category Code. Premphasis. If set, filter premphasis is 50/15 s. If clear, premphasis is none. Copyright. When clear, copyright is asserted. If clear, copyright is not asserted. #Audio valid. When clear, the data routed to the S/PDIF transmitter contains valid PCM data. For transmitting all other compressed data formats, the #Audio bit must be set. 0000h.
DS315PP2
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CS4298
6.1.37 Vendor ID1 (Index 7Ch)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
F7
F6
F5
F4
F3
F2
F1
F0
S7
S6
S5
S4
S3
S2
S1
S0
F[7:0]
First Character of Vendor ID. 43h - ASCII `C' character. S[7:0] Second Character of Vendor ID. 52h - ASCII `R' character. Read-only data4352h.
6.1.38 Vendor ID2 (Index 7Eh)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
T7
T6
T5
T4
T3
T2
T1
T0
PID2
PID1
PID0
RID2
RID1
RID0
T[7:0]
Third Character of Vendor ID. 59h - ASCII `Y' character. PID[3:0] Part ID. See Table10 below. RID[2:0] Revision. See Table10 below. Read-only data5923h.
The two Vendor ID registers provide a means to determine the manufacturer of the AC '97 Codec. The first three bytes of the ID registers contain the ASCII code for the first 3 letters of Crystal (CRY). The final byte of the Vendor ID2 register is divided into a Part ID field and a Revision field.Table 10 lists the Part ID's defined to date.
PID3-PID0
000 001 010 010 011
Part Name
CS4297 CS4297A CS4294 Rev C * CS4298 CS4299
* D3 set Table 10. Reg. 7Eh Defined Part ID's
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CS4298
7. ANALOG HARDWARE DESCRIPTION
The analog hardware consist of a four line-level stereo inputs, two selectable mono microphone inputs, two mono inputs, a mono output, and dual, independent stereo line outputs. This section describes the analog hardware needed to interface with these pins. 7.1 Line-Level Inputs The analog inputs consist of four stereo analog inputs and four mono inputs. As shown in Figure 8, the input to the ADCs comes from the Input Mux which selects one of the following: Phone (Mono), Aux, Video, CD, Mic1 or Mic2 (Mono), Line, Stereo Output Mix, or the Mono Output Mix (Mono). Unused analog inputs should be connected together and then connected through a capacitor to analog ground or tied to the Vrefout line directly. The analog input mixer is designed to accommodate five stereo inputs and one mono input. These inputs are: a stereo line-level input (LINE), a mono microphone input (MIC), a stereo CD-ROM input (CD), a stereo auxiliary line-level input (AUX), and the PCM output from the DACs. Each of the stereo inputs has separate volume controls for each channel and one mute control for each left/right pair. The mono microphone input has one mute and one volume control. The inputs to the output mixer are: the input mixer output, the PC Beep mono input, and the Phone mono input. All analog inputs to the CS4298, including CD_GND, should be capacitively coupled to the input pins. Since many analog levels can be as large as 2 VRMS, the circuit shown in Figure 10 can be used to attenuate the analog input by 6 dB (to 1 VRMS) which is the maximum voltage allowed for all the stereo line-level inputs: LINE_IN, AUX_IN, and VIDEO_IN. The CD line-level inputs have an extra pin, CD_GND, which provides a pseudo-differential input for both CD_L and CD_R. This pin takes the common-mode noise out of the CD inputs when connected to the ground coming from the CD analog source. Connecting the CD pins as shown in Figure 11 provides extra attenuation of common mode noise coming from the CDROM drive, thereby producing a higher quality signal. One percent resistors are recommended since the better the resistors match, the better the common-mode attenuation of unwanted signals. If CD is not used, the inputs should be connected through AC capacitors to analog ground or connected to Vrefout.
6.8 k
1.0 F R 1.0 F L
(All resistors 1%)
6.8 k 3.4 k 6.8 k 6.8 k
1.0 F 2.0 F 1.0 F 6.8 k CD_L CD_GND CD_R
6.8 k 6.8 k
6.8 k
3.4 k
Figure 10. Line Inputs
Figure 11. Differential CDROM In
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7.2 Microphone Level Inputs The microphone level inputs, MIC1 and MIC2, include a selectable -34.5 dB to +12 dB gain stage for interfacing to an external microphone. An additional 20 dB gain block is also available. Figure 12 illustrates a single-ended microphone input buffer circuit that will support lower gain mics. The circuit in Figure 12 supports dynamic mics and phantom-powered mics that use the right channel (ring) of the jack for power.. Line Level Outputs The analog output section provides a stereo line-level output and an alternate stereo line-level output. LINE_OUT_L, LINE_OUT_R, ALT_LINE_OUT_L, and ALT_LINE_OUT_R outputs should be capacitively coupled to external circuitry. The mono output, MONO_OUT, can be used as either a sum of the left and right output channels attenuated by 6 dB to prevent clipping at full scale or the selected MIC_IN signal. The mono out channel can be used to drive the PC internal mono speaker using an appropriate drive circuit. This approach allows the traditional PC sounds to be integrated with the rest of the audio system. The mute control is independent of the line outputs allowing the mono channel to mute the speaker without muting the line outputs. Each of the 5 analog outputs, if used in the design, require 680 pF or larger NPO dielectric capacitors between the corresponding pin and AGND. Each analog output is DC biased up to the Vrefout voltage signal reference which is nominally 2.2 V. This requires that the output either be AC coupled to external circuitry (AC load must be greater than 10 k) or DC coupled to a buffer op-amp biased at the Vrefout voltage (see Figure 13 for the recommended headphone op-amp circuit).
+5 VA +5 VA 8 1 4 68 k AGND AGND 100 k 2.7 k 4 3 5 2 1 220 pF AGND CGND 220 pF +1 2 AGND 47 k 6.8 k 10 F
AGND
7.3
U1A 3 MC33078D + 2 -
47 k
+1 2
10 F
47 k
AGND
47 k AGND 0.068 F X7R +5 VA U1B 8 MC33078D 5+ 1 F 7 6 MIC1 X7R 4
220 pF
Figure 12. PC `99 Microphone Pre-amplifier
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7.4 Consumer IEC-958 Digital Interface (S/PDIF) The CS4298 supports the industry standard IEC-958 consumer digital interface. Sometimes this standard is referred to as S/PDIF, which refers to an older version of this standard. This output provides an interface, external to the PC, for storing digital CD-ROM) or playing digital audio from digital speakers. Figure 14 illustrates the circuit necessary for implementation of the IEC-958 consumer interface. The CS4298 is capable of directly driving the voltage divider for the 75 interface. An optional current driver is shown when an increase of the transmission range of the coaxial circuitry is required. An optional fiber optic circuit may be connected directly to the CS4298. Miscellaneous Analog Signals The AFILT1 and AFILT2 pins must have a 1000 pF NPO capacitor (must not be smaller than 390 pF) to analog ground. These capacitors, along with an internal resistor, provide a single-pole lowpass filter at the inputs to the ADCs. By placing these filters at the input to the ADCs, low-pass filters at each analog input pin are not necessary. The REFFLT pin lowers the noise of the internal voltage reference. A 1 F (must not be greater than 1 F) and 0.1 F capacitor to analog ground should be connected with a short, wide trace to this pin. No other connection should be made, as any coupling onto this pin will degrade the analog performance of the Codec. Likewise, digital signals should be kept away from REFFLT for similar reasons.
7.5
2 3
TDA1308
+ 22pF NPO
1 220F +
10
HP_OUT_R
ELEC
1/4 WATT
ALT_LINE_OUT_R ALT_LINE_OUT_L
1 2
27k
4 3
1 2
4 3
39k
220F + ELEC
10
HP_OUT_L
680pF 680pF
22pF
1/4 WATT
NPO
AGND
NPO
6
NPO +
TDA1308
47K
7
Vrefout
5
43
0.1F Y5V
1.0F Y5V
12
AGND AGND
Figure 13. Headphones Driver
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The Vrefout pin is typically 2.2 V and provides a common mode signal for single-supply external circuits. Vrefout only supports light DC loads and should be buffered if AC loading is needed. For typical use, a 0.1 F in parallel with a 1 F capacitor should be connected to Vrefout. 7.6 Power Supplies The power supplies providing analog power should be as clean as possible to minimize coupling into the analog section which could degrade analog performance. The pins AVdd1 and AVdd2 supply power to all the analog circuitry on the CS4298. This 5 Volt analog supply should be generated from a voltage regulator (7805 type) connected to a +12 Volt supply. This helps isolate the analog circuitry from noise typically found on +5 V digital supplies which power many digital circuits in a PC environment. A typical voltage regulator circuit for analog power using an MC78M05CDT is shown in Figure 15. The digital power pins DVdd1 and DVdd2 should be connected to the same digital supply as the AC '97 Controller's AC-Link interface. Since the digital interface on the CS4298 may operate at either 3.3 V or 5 V, proper connection of these pins will depend on the digital power supply of the AC '97 Controller. connections (vias). The AC-Link digital interface connection traces should be routed
+5 V PCI
0.1 F 1 DGND SPDIFO 2 VCC 5 1 374 GND SN75179D 4 2
DGND
J-RCA-R4-PCB 2 1 90.9 1 4 5 8 1 2
.1F
+5V_PCI SPDIFO 4
5
DGND
3 8.2K
2 1 6
TOTX-173
DGND
DGND
DGND
DGND
Figure 14. IEC-958 Interface Examples
+12VD MC78M05CDT 1 + ELEC 10F IN GND 2 Y5V 0.1F OUT 3
+5VA
+ ELEC 10F
Y5V 0.1F
DGND
AGND
Figure 15. Voltage Regulator
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such that digital ground plane lies underneath these signals (on the internal ground layer) from the AC '97 Controller continuously to the CS4298. 7.7 Hybrid Interface Figure 16 indicates the required components for the secondary side of the hybrid circuity required for the CS4298. The multiple configurations required for the line interface are beyond the scope of this document. Please contact Crystal applications engineering for additional information. .
TX+ Rb1 10 k 1% R2_1 RX+ 6650 1% Cblock 47 F T1 671-8039
Rt1 140 1%
Caa 1000 pF
Co_lpf 0.033 F
Line Interface
Line
MIDCOM R2_2 RX6650 1% Rb2 10 k 1% TXRt2 140 1%
Figure 16. Hybrid Circuit Secondary
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8. PIN DESCRIPTIONS
FLTI FLTO GPIO9 GPIO8 GPIO7/TP3 GPIO6/TP2 GPIO5/TP1 GPIO4/TP0 GPIO3 GPIO2 GPIO1 GPIO0 DVdd1 XTL_OUT XTL_IN DVss1 SDATA_OUT BIT_CLK DVss2 SDATA_IN DVdd2 SYNC RESET# S/PDIF_OUT BCM# AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND CD_R
57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
FLT3D AVss5 HRXHRX+ AVss4 HTXHTX+ AVdd4 AVss3 MTXMTX+ AVdd3 MRXMRX+ ID0# ALT_LINE_OUT_R ALT_LINE_OUT_L AVss2 AVdd2 LINE_OUT_R LINE_OUT_L ID1# AFLT2 AFLT1 Vrefout REFFLT AVss1 AVdd1 LINE_IN_R LINE_IN_L MIC2 MIC1
CS4298-KQ
64-pin TQFP Top View
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8.1 g2 Digital I/O Pins RESET# - AC '97 Chip Reset, Input This active low signal is the asynchronous Cold Reset input to the CS4298. The CS4298 must be reset before it can enter normal operating mode. When the PR4 bit of register 26h is set, the RESET# rising edge will be used as an AC `97 2.1 Warm Reset only, preserving register values. SYNC - AC-link Serial Port Sync pulse, Input This signal is the serial port timing signal for the AC-link of the CS4298. Its period is the reciprocal of the sample rate of the CS4298, 48 kHz. This signal is generated by the AC '97 Controller and is synchronous to BIT_CLK. SYNC is also an asynchronous input when the CS4298 is in a PR4 powerdown state and is configured as a primary codec. A series terminating resistor of 47 should be connected on this signal close to the device driving the signal. BIT_CLK - AC-link Serial Port Master Clock, Input/Output This input/output signal controls the master clock timing for the AC-link. In codec primary mode, this signal is an output 12.288 MHz clock signal which is divided down by two from the XTL_IN input clock pin. In codec secondary mode, this signal is an input which controls the AC-link serial interface. In BIT_CLK mode, this signal generates all internal clocking including the AC-link serial interface timing. A series terminating resistor of 47 should be connected on this signal close to the CS4298 in primary mode or close to the BIT_CLK source if in secondary mode. SDATA_OUT - AC-link Serial Data Input Stream to AC `97, Input This input signal transmits the control information and digital audio output streams to be sent to the DACs. The data is clocked into the CS4298 on the falling edge of BIT_CLK. A series terminating resistor of 47 should be connected on this signal close to the device driving the input. SDATA_IN - AC-link Serial Data Output Stream from AC `97, Output This output signal transmits the status information and digital audio input streams from the ADCs. The data is clocked out of the CS4298 on the rising edge of BIT_CLK. A series terminating resistor of 47 should be connected on this signal as close to the CS4298 as possible. XTL_IN - Crystal Input This pin accepts either a crystal, with the other pin attached to XTL_OUT, or an external CMOS clock. XTL_IN must have a crystal or clock source attached for proper operation except when operating in BIT_CLK mode. The crystal frequency must be 24.576 MHz and designed for fundamental mode, parallel resonance operation.
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XTL_OUT - Crystal Output This pin is used for a crystal placed between this pin and XLT_IN. If an external clock is used on XTL_IN or the codec is in BIT_CLK mode, this pin must be left floating with no traces or components connected to it. ID1#, ID0# - Codec ID, Inputs These pins select the codec ID and mode of operation for the CS4298. They are sampled after the rising edge of RESET# and not used after. These inputs have internal 100 k pull-ups and should be left floating for a logic 0 or tied to analog ground for a logic 1. The pins utilize inverted logic, so the condition of both pins floating sets the codec to primary mode while any other combination sets the codec to a secondary mode. In primary mode, the codec is always clocked from an external crystal or an external oscillator connected to the XTL_IN and/or XTL_OUT pins with BIT_CLK as an output. In secondary mode, the clocking mechanism is determined by the state of the BCM# pin with BIT_CLK always being an input. BCM# - BIT_CLK Mode, Input This pin selects the secondary mode clocking mechanism. BCM# is sampled after the rising edge of RESET# and not used after. In codec secondary mode (ID1# and or ID0# grounded), grounding this input will select BIT_CLK mode. In this mode, BIT_CLK is defined as an input and all internal timing will be derived from the BIT_CLK signal and no connections should be made to XTAL_IN and XTAL_OUT. When BCM# is floating, all timing will be derived from the XTAL_IN pin. In this case, XTAL_IN must be syncronous to BIT_CLK. In primary mode, BCM# must be left floating. S/PDIF_OUT - Sony/Phillips Digital Interface, Output This pin generates IEC 958 consumer compatible (S/PDIF) digital output from the CS4298 using output slots 6 and 9 when the SPDIF_EN bit in register 68h is set. For use with consumer audio equipment, the output may be used to drive an RS422A compliant interface through an isolation transformer, or a CP-1201 compliant interface through a TOSLINK module. When S/PDIF_OUT is not being used this output is driven to a logic `0'. GPIO[9:0] - General Purpose Input/Output These GPIO pins are used to control modem DAAs and other discrete digital functions. When a GPIO pin is configured as an input, it behaves as a Schmitt trigger input with 350 mV of hysteresis at 5 V and 220 mV of hysteresis at 3.3 V. When a GPIO pin in configured as an output, it may function as a normal CMOS output (4 mA drive) or as an open drain output. GPIO pins power up in the high impedance state (tri-state).
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8.2 Analog I/O Pins
MIC1 - Analog Mono Source, Input This analog input is a monophonic source to the analog output mixer. It is intended to be used as a desktop microphone connection to the audio subsystem. This input is MUX selectable to the input mixer with the MIC2 input source. The maximum allowable input is 1 VRMS (sinusoidal). If the 20 dB internal boost is enabled, the maximum allowable input is 100 mVRMS (sinusoidal). This input is internally biased at the Vrefout voltage reference and requires AC coupling to external circuitry. If this input is not used, it should be AC coupled to analog ground. MIC2 - Analog Mono Source, Input This analog input is a monophonic source to the analog output mixer. It is intended to be used as an alternate microphone connection to the audio subsystem. This input is MUX selectable to the input mixer with the MIC1 input source. The maximum allowable input is 1 VRMS (sinusoidal). If the 20 dB internal boost is enabled, the maximum allowable input is 100 mVRMS (sinusoidal).This input is internally biased at the Vrefout voltage reference and requires AC coupling to external circuitry. If this input is not used, it should be AC coupled to analog ground. LINE_IN_L and LINE_IN_R- Analog Line Source, Inputs These inputs form a stereo input pair to the CS4298. The maximum allowable input is 1 VRMS (sinusoidal). These inputs are internally biased at the Vrefout voltage reference. AC coupling to external circuitry is required. If these inputs are not used, they should both be connected to the Vrefout pin or both AC coupled, with separate AC coupling caps, to analog ground. CD_L and CD_R - Analog CD Source, Inputs These inputs form a stereo input pair to the CS4298. It is intended to be used for the Red Book CD audio connection to the audio subsystem. The maximum allowable input is 1 VRMS (sinusoidal). These inputs are internally biased at the Vrefout voltage reference. AC coupling to external circuitry is required. If these inputs are not used, they should both be connected to the Vrefout pin or both AC coupled, with separate AC coupling caps, to analog ground. CD_GND - Analog CD Common Source, Input This analog input is used to remove common mode noise from Red Book CD audio signals. The impedance on the input signal path should be one half the impedance on the CD_L and CD_R input paths. This pin requires AC coupling to external circuitry. If this input is not used, it should be connected to the Vrefout pin or AC coupled to analog ground.
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CS4298
VIDEO_L and VIDEO_R - Analog Video Audio Source, Inputs These inputs form a stereo input pair to the CS4298. It is intended to be used for the audio signal output of a video device. The maximum allowable input is 1 VRMS (sinusoidal). These inputs are internally biased at the Vrefout voltage reference. AC coupling to external circuitry is required. If these inputs are not used, they should both be connected to the Vrefout pin or both AC coupled, with separate AC coupling caps, to analog ground. AUX_L and AUX_R - Analog Auxiliary Source, Inputs These inputs form a stereo input pair to the CS4298. The maximum allowable input is 1 VRMS (sinusoidal). These inputs are internally biased at the Vrefout voltage reference. AC coupling to external circuitry is required. If these inputs are not used, they should both be connected to the Vrefout pin or both AC coupled, with separate AC coupling caps, to analog ground. LINE_OUT_L and LINE_OUT_R - Analog Line Level Outputs These signals are analog outputs from the stereo output mixer. The full scale output voltage for output is nominally 1 VRMS and is internally biased at the Vrefout voltage reference. It is required to either AC couple these pins to external circuitry or DC couple them to a buffer opamp biased at the Vrefout voltage. These pins need a 680 pF NPO capacitor attached to analog ground. ALT_LINE_OUT_L and ALT_LINE_OUT_R - Analog Alternate Line Level Outputs These signals are analog outputs from the stereo output mixer. The full scale output voltage for each output is nominally 1 VRMS and is internally biased at the Vrefout voltage reference. It is required to either AC couple these pins to external circuitry or DC couple them to a buffer opamp biased at the Vrefout voltage. These pins need a 680 pF NPO capacitor attached to analog ground. 8.3 Filter and Reference Pins REFFLT - Internal Reference Voltage, Input This is the voltage reference used internal to the part. A 0.1 F and a 1 F (must not be larger than 1 F) capacitor with short, wide traces must be connected to this pin. No other connections should be made to this pin. Vrefout - Voltage Reference, Output All analog inputs and outputs are centered around Vrefout which is nominally 2.2 Volts. This pin may be used to level shift external circuitry, however any external loading should be buffered. AFLT1 - Left Channel Antialiasing Filter Input This pin needs a 390 pF NPO capacitor attached to analog ground. AFLT2 - Right Channel Antialiasing Filter Input This pin needs a 390 pF NPO capacitor attached to analog ground.
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FLTI - 3D Filter Input A 1000 pF capacitor must be attached between this pin and FLTO if the 3D function is used. FLTO - 3D Filter Output A 1000 pF capacitor must be attached between this pin and FLTI if the 3D function is used. FLT3D - 3D Filter A 0.01 F capacitor must be attached from this pin to AGND if the 3D function is used. 8.4 Modem/Telephony
MRX+, MRX- - Modem Line Differential Receive, Inputs This differential input receive pair connects to a 2- to 4-wire hybrid converter or an integrated DAA and is used to sample the analog phone line signal. The maximum full scale differential input is 3.0 Vp-p. These pins may be used in single ended fashion by connecting the input to MRX+ and AC-grounding the MRX- pin, or by tying one of the two inputs to Vrefout to provide DC-biasing. HRX+, HRX- - Handset Differential Receive, Inputs This differential input receive pair connects to a 2- to 4-wire hybrid converter and is used to communicate with the local handset. These input pins may also be used to interface to a second telephone line. The maximum full scale differential input is 3.0 Vp-p. These pins may be used in single ended fashion by connecting the input to HRX+ and AC-grounding the HRX- pin, or by tying one of the two inputs to Vrefout to provide DC-biasing. MTX+, MTX- - Modem Line Differential Transmit, Outputs This differential transmit output pair connects the a 2- to 4-wire hybrid converter or an integrated DAA and is used to transmit over the analog phone line. The maximum full scale differential output is 5.6 Vp-p (MTX+ to MTX-). Each output pin is internally biased at the Vrefout voltage. These pins may be used in single ended fashion by using one leg of the differential output pair. The maximum output for each pin is 2.8 Vp-p or 1.0 Vrms. HTX+, HTX- - Handset Differential Transmit, Outputs This differential transmit output pair connects the a 2- to 4-wire hybrid converter or an integrated DAA and is used to transmit over the analog phone line. The maximum full scale differential output is 5.6 Vp-p (HTX+ to HTX-). Each output pin is internally biased at the Vrefout voltage. These pins may be used in single ended fashion by using one leg of the differential output pair. The maximum output for each pin is 2.8 Vp-p or 1.0 Vrms.
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8.5 Power Supplies
DVdd1, DVdd2 - Digital Supply Voltage These pins provide the digital supply voltage for the AC-link section of the CS4298. These pins may be tied to +5 V digital or to +3.3 V digital. The CS4298 and digital controller's AC-link should share a common digital supply. DVss1, DVss2 - Digital Ground These pins are the digital ground connection for the AC-link section of the CS4298. These pins should be isolated from analog ground currents. AVdd1, AVdd2, AVdd3, AVdd4 - Analog Supply Voltage These pins provide the analog supply voltage for the analog and mixed signal sections of the CS4298. These pins must be tied to +5 V analog supply. It is strongly recommended that +5 V be generated from a voltage regulator to ensure proper supply currents and noise immunity from the rest of the system. AVss1, AVss2, AVss3, AVss4, AVss5 - Analog Ground These pins are the ground connection for the analog, mixed signal, and substrate sections of the CS4298. These pins should be isolated from digital ground currents.
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9. PARAMETER AND TERM DEFINITIONS
AC '97 Specification Refers to the Audio Codec `97 Component Specification Ver 2.1 published by Intel (R) Corporation []. AC '97 Controller or Controller Refers to the control chip which interfaces to the Codec's AC-link. This has been also called DC '97 for Digital Controller `97 []. AC '97 Registers or Codec registers Refers to the 64-field register map defined in the AC '97 Specification. ADC Refers to a single Analog-to-Digital converter in the Codec. "ADCs" refers to the stereo pair of Analog-to-Digital converters. DAC A single Digital-to-Analog converter in the Codec "DACs" refers to the stereo pair of Digitalto-Analog converters. SRC Sample Rate converter. Converts data derived at one sample rate to a differing sample rate. Codec Refers to the chip containing the ADCs, DACs, and analog mixer. In this data sheet, the Codec is the CS4297A9. FFT Fast Fourier Transform. Resolution The number of bits in the output words to the DACs, and in the input words to the ADCs. Differential Nonlinearity The worst case deviation from the ideal code width. Units in LSB. dB FS A dB FS is defined as dB relative to full-scale. The "A" indicates an A weighting filter was used.
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CS4298
Frequency Response (FR) FR is the deviation in signal level verses frequency. The 0 dB reference point is 1 kHz. The amplitude corner, Ac, lists the maximum deviation in amplitude above and below the 1 kHz reference point. The listed minimum and maximum frequencies are guaranteed to be within the Ac from minimum frequency to maximum frequency inclusive. Dynamic Range (DR) DR is the ratio of the RMS full-scale signal level divided by the RMS sum of the noise floor, in the presence of a signal, available at any instant in time (no change in gain settings between measurements). Measured over a 20 Hz to 20 kHz bandwidth with units in dB FS A. Total Harmonic Distortion plus Noise (THD+N) THD+N is the ratio of the RMS sum of all non-fundamental frequency components, divided by the RMS full-scale signal level. It is tested using a -3 dB FS input signal and is measured over a 20 Hz to 20 kHz bandwidth with units in dB FS. Signal to Noise Ratio (SNR) SNR, similar to DR, is the ratio of an arbitrary sinusoidal input signal to the RMS sum of the noise floor, in the presence of a signal. It is measured over a 20 Hz to 20 kHz bandwidth with units in dB. S/PDIF Sony/Phillips Digital Interface. This interface was established as a means of digitally interconnecting consumer audio equipment. The documentation for S/PDIF has been superseded by the IEC-958 consumer digital interface document. Interchannel Isolation The amount of 1 kHz signal present on the output of the grounded AC-coupled line input channel with 1 kHz, 0 dB, signal present on the other line input channel. Units in dB. Interchannel Gain Mismatch For the ADCs, the difference in input voltage to get an equal code on both channels. For the DACs, the difference in output voltages for each channel when both channels are fed the same code. Units in dB. PATHS A-D: Analog in, through the ADC, onto the serial link. D-A: Serial interface inputs through the DAC to the analog output. A-A: Analog in to Analog out (analog mixer).
10. REFERENCES
Intel, Audio Codec `97 Component Specification, Revision 2.1, May 22,1998. http://developer.intel.com/pc-supp /platform/ac97/
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11. PACKAGE DIMENSIONS
64L TQFP PACKAGE DRAWING
E E1
D D1
1
e
B A A1
L
INCHES MIN MAX --0.063 0.002 0.006 0.007 0.011 0.461 0.484 0.390 0.398 0.461 0.484 0.390 0.398 0.016 0.024 0.018 0.030 0.000 7.000 * Nominal pin pitch is 0.50 mm DIM A A1 B D D1 E E1 e* L Controlling dimension is mm. JEDEC Designation: MS026 MILLIMETERS MIN MAX --1.60 0.05 0.15 0.17 0.27 11.70 12.30 9.90 10.10 11.70 12.30 9.90 10.10 0.40 0.60 0.45 0.75 0.00 7.00
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